SONET/SDH Low Jitter System Synchronizer
ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer
Data Sheet
Features
• Supports the requirements of Telcordia GR-253 ...
Description
ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer
Data Sheet
Features
Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks
Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
Provides two DPLLs which are independently configurable through a serial software interface
DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range
DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other general purpose clocks
Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
June 2008
Ordering Information
ZL30116GGGV2 100 Pin CABGA Trays ZL30116GGG2V2100 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper -40oC to +85oC
Supports master/slave configuration for AdvancedTCATM
Configurable input to output delay and output to output phase alignment
Optional external feedback path provides dynamic input to output delay compensation
Provides 3 sync inputs for output fram...
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