GS88136B

www.DataSheet4U.com GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) 100-pin TQFP & 165-bump BGA Commercial Temp Industrial Temp Features IEEE 1149.1 JTAG-compatible Boundary Scan 2.5 V or 3.3 V +10%/–10% core power supply 2.5 V or 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 100-lead TQFP and 165-bump BGA packages RoHS-compliant 100-lead TQFP and 165-bump BGA packages available 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 333 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. SCD Pipelined Reads The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte wri...