MT28F322P3

www.DataSheet4U.com PRELIMINARY‡ 2 MEG x 16 ASYNC/PAGE FLASH MEMORY FLASH MEMORY MT28F322P3 Low Voltage, Extended Temperature FEATURES Flexible dual-bank architecture Support for true concurrent operation with zero latency Read bank a during program bank b and vice versa Read bank a during erase bank b and vice versa Basic configuration: Seventy-one erasable blocks Bank a (8Mb for data storage) Bank b (24Mb for program storage) VCC, VCCQ, VPP voltages 2.7V (MIN), 3.3V (MAX) VCC 2.2V (MIN), 3.3V (MAX) VCCQ 3.0V (TYP) VPP (in-system PROGRAM/ERASE) 12V ±5% (HV) VPP tolerant (factory programming compatibility) Random access time: 70ns @ 2.7V VCC Page Mode read access Eight-word page Interpage read access: 70ns @ 2.7V Intrapage read access: 30ns @ 2.7V Low power consumption (VCC = 3.3V) Asynchronous/interpage READ < 15mA Intrapage READ < 7mA WRITE < 20mA (MAX) ERASE < 25mA (MAX) Standby < 15µA (TYP), 50µA (MAX) @ 3.3V Automatic power save (APS) feature Enhanced write and erase suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank Dual 64-bit chip protection registers for security purposes Cross-compatible command support Extended command set Common flash interface PROGRAM/ERASE cycle 100,000 WRITE/ERASE cycles per block Fast programming algorithm VPP = 12V ±5% BALL ASSIGNMENT 48-Ball FBGA 1 A B C D E F A13 2 A11 3 A8 4 VPP 5 WP# 6 A19 7 A7 8 A4 A14 A10 WE# RS...