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MT90840
Distributed Hyperchannel Switch
Data Sheet Features
• Time slot interchange function between eight pairs of ST-BUS/GCI/MVIP ™ streams (512 channels) and parallel data port Programmable data rates on the parallel port (19.44, 16.384, or 6.480 Mbyte/s) Programmable data rates on the serial port (2.048 Mbps, 4.096 Mbps or 8.192 Mbps) Supports star and point-to-point connections, and unidirectional or bidirectional ring topologies for distributed systems Input-to-output bypass function on the parallel data port for use in add/drop applications Provides elastic buffer at parallel input port in the receive direction Provides byte switching for up to 2430 channels Per-channel direction control on the serial port side Per-channel message mode and high-impedance control on both parallel and serial port sides 8-bit multiplexed microprocessor port compatible with Intel and Motorola microcontrollers Guarantees frame integrity when switching nX64 wideband channels such as ISDN H0 channel Provides external control lines allowing fast parallel interface to be shared with other devices
ISSUE 3 July 2002
• • •
Ordering Information MT90840AL 100 Pin PQFP MT90840AP 84 Pin PLCC -40 °C to 85 °C • • Diagnostic alarm functions and clock phase-status word for clock monitoring IEEE 1149 (JTAG) boundary scan port
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Applications
• Bridging ST-BUS/MVIP buses to high speed Time Division Multiplexed backplanes at SONET rates (STS-1, STS-3) High speed isochronous backbones for distributed PBX and LAN systems Switch platforms of up to 2430 channels with guaranteed frame integrity for wideband channels Serial bus control and monitoring Data multiplexing High speed communications interface
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PDo0 PDo7 CTo0-3 PDi0 PDi7
8 Output Mux & Drivers 4
Multiple Pages of 512 Position TX Path Data Memory 16 2430 Position TX Path Connection Memory 8
8
Serial to Parallel &
Bidirectional I/O Driver
STi0 STi7
8 8
Parallel to Serial Converters
Multiple Pages of 2430-Byte RX Path Data Memory 15
Bidirectional I/O Driver
STo0 STo7
PCKR PCKT RES PPFRi PPFTi/o F0i/o
Timing Control Unit
512 Position RX Path Connection Memory
JTAG
5
TEST Pins
CPU Interface
Internal Registers 8 8 VSS
R/W\WR
SPCKo
C4/8R1
C4/8R2
AD0-7
DS/RD
Figure 1 - Functional Block Diagram
AS/ALE
DTA
VDD
IRQ
CS
2-231
MT90840
VSS NC IC RES IRQ DTA CS AS/ALE DS/RD VDD VSS R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VDD
Data Sheet
46
48
34
36
38
40
42
44
50
VDD STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 C4/8R1 F0i/o C4/8R2 VSS VDD NC NC CTo3 CTo2 CTo1 CTo0
VSS
10
8
6
4
2
84
82
80
78
12 14
76
74 72
16 18 20 22 24 26 28 30 32
70 68 66
84 PIN PLCC
64 62 60 58 56 52 54
VSS STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 SPCKo VSS VDD TDO TMS TCK TRST TDI PPFRi PCKT PCKR VDD
NC NC NC NC NC VDD VSS CTo0 CTo1 CTo2 CTo3 VDD VSS C4/8R2 F0i/o C4/8R1 STi7 STi6 STi5 STi4 STi3 STi2 STi1 STi0 VDD VSS NC NC NC NC 80 82 48 84 46 86 44 88 42 90 92 94 36 96 34 98 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 32 30 100 PIN PQFP 40 38 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50
VDD PDo7 PDo6 PDo5 PDo4 PDo3 PDo2 PDo1 PDo0 PPFTi/o VSS VDD PDi7 PDi6 PDi5 PDi4 PDi3 PDi2 PDi1 PDi0 VSS
PDo7 PDo6 PDo5 PDo4 PDo3 PDo2 PDo1 PDo0 PPFTi/o VSS VDD PDi7 PDi6 PDi5 PDi4 PDi3 PDi2 PDi1 PDi0 VSS
NC IC RES IRQ DTA CS AS/ALE DS/RD VDD VSS R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC
2-232
NC NC NC NC VDD PCKR PCKT PPFRi TDI TRST TCK TMS TDO VDD VSS SPCKo STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 VSS VDD NC NC NC NC
Figure 2 - Pin Connections
Data Sheet
Pin Description
Pin # 84 3 100 43 Name DS/RD Description
MT90840
Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, an active high input which works with CS to enable read and write operation. In Intel/ National multiplexed-bus mode this pin is RD, an active low input which enables a read-cycle and configures the data bus lines (AD0-AD7) as outputs. Address Strobe / Address Latch Enable (Input). Falling edge is used to sample address into the Address Latch circuit. Chip Select (Input). Active low input enabling a microprocessor read or write of control or status registers. Data Acknowledgment (Active Low Output). Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. Note that CPU read/writes from/to the Data and Connection memories occur on the serial or parallel port clock edges, and DTA will not change state if the clock is halted. Interrupt Request (Active High Output). Output indicates that the MT90840 has detected an alarm condition. The indication of the specific condition can be read in the ALS (Alarm Status) Register. The CPU should read ALS, identify the source for the interrupt and then rewrite the mask bits to re-enable the IRQ signal. RESET (Schmitt Input). A.