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HY57V64420HG Dataheets PDF



Part Number HY57V64420HG
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4 Banks x 4M x 4Bit Synchronous DRAM
Datasheet HY57V64420HG DatasheetHY57V64420HG Datasheet (PDF)

www.DataSheet4U.com HY57V64420HG 4 Banks x 4M x 4Bit Synchronous DRAM DESCRIPTION The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4. HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths ar.

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www.DataSheet4U.com HY57V64420HG 4 Banks x 4M x 4Bit Synchronous DRAM DESCRIPTION The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4. HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • • • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation • • • • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst • - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks • • ORDERING INFORMATION Part No. HY57V64420HGT-5/55/6/7 HY57V64420HGT-K HY57V64420HGT-H HY57V64420HGT-P HY57V64420HGT-S HY57V64420HGLT-5/55/6/7 HY57V64420HGLT-K HY57V64420HGLT-H HY57V64420HGLT-P HY57V64420HGLT-S Clock Frequency 200/183/166/143MHz 133MHz 133MHz 100MHz 100MHz 200/183/166/143MHz 133MHz 133MHz 100MHz 100MHz Power Organization Interface Package Normal 4Banks x 4Mbits x4 LVTTL 400mil 54pin TSOP II Low power This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Nov. 01 1 HY57V64420HG PIN CONFIGURATION VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 54pin TSOP II 400mil x 875mil 0.8mm pin pitch PIN DESCRIPTION PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection RAS, CAS, WE DQM DQ0 ~ DQ3 VDD/VSS VDDQ/VSSQ NC Rev. 0.4/Nov. 01 2 HY57V64420HG FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 4 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter CLK Row active 4Mx4 Bank3 Row Pre Decoders 4Mx4 Bank 2 X decoders 4Mx4 Bank 1 X decoders 4Mx4 Bank 0 X decoders Sense AMP & I/O Gate CKE CS State Machine RAS CAS WE DQM X decoders I/O Buffer & Logic refresh Column Active Memory Cell Array DQ0 DQ1 DQ2 DQ3 Column Pre Decoders Y decoders Bank Select Column Add Counter A0 A1 Address buffers A11 BA0 BA1 Address Registers Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control Rev. 0.4/Nov. 01 3 HY57V64420HG ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature ⋅ Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 ⋅ 10 Rating °C °C V V mA W °C ⋅ Sec Unit Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol .


HSMT-C265 HY57V64420HG IRLL014


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