SY10H606

Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS REGISTERED HEX TTL-TO-PECL SY10H606 SY1S0YH10600H6606 SY100H606 FEATURES DESCRIPTION s Differential 50Ω ECL outputs s Choice between differential PECL or TTL clock input s Single +5V power supply s VBB output for single-ended use s Multiple power and ground pins to minimize noise s Specified within-device skew s Fully compatible with MC10H/100H606 s Available in 28-pin PLCC package The SY10/100H606 are 6-bit, registered, single supply TTL-to-PECL translators. The devices feature differential PECL outputs as well as a choice between either a differential PECL clock input or a TTL clock input. The asynchronous master reset control is a PECL level input. With its differential ECL outputs and TTL inputs, the H606 device is ideally suited for the transmit function of a HPPI bus-type board-to-board interface application. The on-chip registers simplify the task of synchronizing the data between the two boards. The device is available in either ECL standard: the 10H device is compatible with 10K logic levels, while the 100H device is compatible with 100K logic levels. BLOCK DIAGRAM Dn CLK CLK TCLK 1 OF 6 BITS DQ CLK R PIN NAMES Pin D0 – D5 CLK, CLK TCLK Qn MR Qn Q0 – Q5 Q0 – Q5 VCCE VCCT GND VBB Function TTL Data Inputs Differential PECL Clock Inputs TTL Clock Input PECL Master Reset Input True PECL Outputs Inverted PECL Outputs PECL VCC (5.0V) TTL VCC (5.0V) TTL/PECL Ground VBB Reference Output (PECL) MR VBB M9999-032906 hbw...