PM5377

www.DataSheet4U.com PM5377 TSE 240 Released Single Chip 96-Port STS-1/STM-0 Cross-Connect FEATURES Implements a 240G memory switch fabric with STS-1/AU-3 switching granularity. 96 ingress and 96 egress STS48/STS-12 ports for a maximum of 4608 STS-1/AU-3 streams in a single device. Supports a single-stage, anycast switching capacity of 240G. DELAY MANAGEMENT Provides a 108 byte FIFO for each ingress port to support 102 byte maximum skew among the input links (1312 ns for 622 Mbit/s links and 328 ns for 2.488 Gbit/s links). Provides 13 delay management (DM) blocks that can be allocated to a subset of devices ports (1 through 25) as either input delay management (DMI) or output delay management (DMO). Each DM block processes a STS-48 signal for an aggregate delay management capacity of 32.5 Gbit/s. Supports ganging of 4 DM blocks to form a delay management group (DMG) capable of processing a STS192 signal. SWITCH PORT CONFIGURATION Each port can be individually configured for 2.488Gbit/s or 622Mbit/s operation. Ingress and egress links of a port can be individually configured. Optionally inserts AIS on ingress links that are out-of-frame. Supports unequipped overwrite, and path AIS overwrite on a per egress port and per egress grain basis. Implements the ESSI Frame layer Each DM block allocated as DMI supports arbitrary frame alignment of an STS-48 ingress signal to the frame alignment of the synchronous switching core. Each DM block allocated as DMO...