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BQ4024Y Dataheets PDF



Part Number BQ4024Y
Manufacturers Benchmarq
Logo Benchmarq
Description Nonvolatile SRAM
Datasheet BQ4024Y DatasheetBQ4024Y Datasheet (PDF)

www.DataSheet4U.com bq4024/bq4024Y 128Kx16 Nonvolatile SRAM Features ® Data retention in the absence of power ® Automatic write-protection during power-up/power-down cycles ® Industry-standard 40-pin 128K x 16 pinout ® Conventional SRAM operation; unlimited write cycles ® 10-year minimum data retention in absence of power ® Battery internally isolated until power is applied General Description The CMOS bq4024 is a nonvolatile 2,097,152-bit static RAM organized as 131,072 words by 16 bits. The .

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www.DataSheet4U.com bq4024/bq4024Y 128Kx16 Nonvolatile SRAM Features ® Data retention in the absence of power ® Automatic write-protection during power-up/power-down cycles ® Industry-standard 40-pin 128K x 16 pinout ® Conventional SRAM operation; unlimited write cycles ® 10-year minimum data retention in absence of power ® Battery internally isolated until power is applied General Description The CMOS bq4024 is a nonvolatile 2,097,152-bit static RAM organized as 131,072 words by 16 bits. The integral control circuitry and lithium energy source provide reliable nonvolatility coupled with the unlimited write cycles of standard SRAM. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC falls out of tolerance, the SRAM is unconditionally writeprotected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The bq4024 uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. The bq4024 requires no external circuitry and is compatible with the industry-standard 2Mb SRAM pinout. Pin Connections NC CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 VSS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC WE A16 A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 Pin Names A0–A16 Address inputs DQ0–DQ15 Data input/output CE OE WE NC VCC VSS Chip enable input Output enable input Write enable input No connect +5 volt supply input Ground Block Diagram 40-Pin DIP Module PN402401.eps Selection Guide Part Number bq4024MA -85 bq4024MA -120 Maximum Access Time (ns) 85 120 Negative Supply Tolerance -5% -5% Part Number bq4024YMA -85 bq4024YMA -120 Maximum Access Time (ns) 85 120 Negative Supply Tolerance -10% -10% Sept. 1992 1 bq4024/bq4024Y Functional Description When power is valid, the bq4024 operates as a standard CMOS SRAM. During power-down and power-up cycles, the bq4024 acts as a nonvolatile memory, automatically protecting and preserving the memory contents. Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD. The bq4024 monitors for VPFD = 4.62V typical for use in systems with 5% supply tolerance. The bq4024Y monitors for VPFD = 4.37V typical for use in systems with 10% supply tolerance. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become high impedance, and all inputs are treated as “don’t care.” If a valid access is in process at the time of power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT, write-protection takes place. As VCC falls past VPFD and approaches 3V, the control circuitry .


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