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ATT3064 Dataheets PDF



Part Number ATT3064
Manufacturers Lucent
Logo Lucent
Description (ATT3000 Series) Field-Programmable Gate Arrays
Datasheet ATT3064 DatasheetATT3064 Datasheet (PDF)

www.DataSheet4U.com Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Features s Description The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of highdensity, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection. Th.

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www.DataSheet4U.com Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Features s Description The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of highdensity, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection. The general structure of an FPGA is shown in Figure 1. The ORCA Foundry for ATT3000 Development System provides automatic place and route of netlists. Logic and timing simulation are available as design verification alternatives. The design editor is used for interactive design optimization and to compile the data pattern that represents the configuration program. The FPGA’s user-logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM, or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at powerup. A serial configuration PROM can provide a very simple serial configuration program storage. * Xilinx, XC3000, and XC3100 are registered trademarks of Xilinx, Inc. High performance: — Up to 270 MHz toggle rates — 4-input LUT delays <2.7 ns User-programmable gate arrays — Unlimited reprogrammability — Easy design iteration through in-system logic changes Flexible array architecture: — Compatible arrays ranging from 1500 to 6000 gate logic complexity — Extensive register, combinatorial, and I/O capabilities — Low-skew clock nets — High fan-out signal distribution — Internal 3-state bus capabilities — TTL or CMOS input thresholds — On-chip oscillator amplifier Standard product availability: — Low-power 0.55 µm CMOS, static memory technology — Pin-for-pin compatible with Xilinx* XC3000* and XC3100* families — Cost-effective for volume production — 100% factory pretested — Selectable configuration modes ORCA™ Foundry for ATT3000 Development System support All FPGAs processed on a QML-certified line Extensive packaging options s s s s s s Table 1. ATT3000 Series FPGAs FPGA ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 Max Logic Gates 1,500 2,000 3,000 4,500 6,000 Typical Gate Range 1,000—1,500 1,500—2,000 2,000—3,000 3,500—4,500 5,000—6,000 Configurable Logic Blocks 64 100 144 224 320 Array 8x8 10 x 10 12 x 12 16 x 14 20 x 16 User I/Os Max 64 80 96 120 144 FlipFlops 256 360 480 688 928 Horizontal Long Lines 16 20 24 32 40 Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 ATT3000 Series Field-Programmable Gate Arrays Data Sheet February 1997 Table of Contents Contents Page Contents Page Features ..................................................................... 1 Description ................................................................. 1 Architecture ................................................................ 3 Configuration Memory................................................ 4 I/O Block ..................................................................... 5 Summary of I/O Options ......................................... 6 Configurable Logic Block ............................................ 7 Programmable Interconnect ....................................... 9 General-Purpose Interconnect ............................. 10 Direct Interconnect ............................................... 11 Long Lines ............................................................ 13 Internal Buses ...................................................... 14 Crystal Oscillator .................................................. 16 Configuration ............................................................ 17 Initialization Phase ............................................... 17 Configuration Data ............................................... 19 Configuration Modes ................................................ 22 Master Mode ........................................................ 22 Peripheral Mode ................................................... 24 Slave Mode .......................................................... 25 Daisy Chain .......................................................... 26 Special Configuration Functions .............................. 27 Input Thresholds ................................................... 27 Readback ............................................................. 27 Reprogram ........................................................... 28 DONE Pull-Up ...................................................... 28 DONE Timing ....................................................... 28 RESET Timing ...................................................... 28 Crystal Oscillator Division .....


ATT3042 ATT3064 ATT3090


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