K7A203200A

www.DataSheet4U.com PRELIMINARY K7A203200A Document Title 64Kx32-Bit Synchronous Pipelined Burst SRAM, 64Kx32 Synchronous SRAM Revision History Rev. No. 0.0 1.0 History Final spec release. Add VDDQ Supply voltage( 2.5V ) Draft Date Nov. 10. 1998 Dec. 02. 1998 Remark Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- December 1998 Rev 1.0 PRELIMINARY K7A203200A FEATURES Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V+0.3V/-0.165V Power Supply. VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. 5V Tolerant Inputs Except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention ; 2 cycle Enable, 1 cycle Disable. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. TTL-Level Three-State Output. 100-TQFP-1420A 64Kx32 Synchronous SRAM 64...