C9870G

www.DataSheet4U.com Approved Product C9870G High Performance Pentium® 4 Clock Synthesizer Product Features Supports Pentium 4 Type CPUs 3.3 Volt Power Supply 10 Copies of PCI Clocks ® 3 Differential CPU Clocks SMBus Support with Read-back Capabilities Spread Spectrum EMI Reduction Dial-a-Frequency™ Features Dial-a-dB™ Features 56 Pin SSOP and TSSOP Package Frequency Table S2 1 1 1 1 0 0 0 0 M M M M S1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 CPU (0:2) 66M 100M 200M 133M 66M 100M 200M 133M Hi-Z TCLK/2 150M 166.6M 3V66 66M 66M 66M 66M 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M 66BUFF(0:2)/ 3V66(0:4) 66IN 66IN 66IN 66IN 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M 66IN/ 3V66-5 66MHz clock input 66MHz clock input 66MHz clock input 66MHZ clock input 66M 66M 66M 66M Hi-Z TCLK/4 50M 55.5M PCI_F PCI 66IN/2 66IN/2 66IN/2 66IN/2 33 M 33 M 33 M 33 M Hi-Z TCLK/8 25M 27.7M REF 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M Hi-Z TCLK 14.318M 14.318M USB/ DOT 48M 48M 48M 48M 48M 48M 48M 48M Hi-Z TCLK/2 48M 48M Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register. Block Diagram XIN XOUT PLL1 CPU_STP# IREF VSSIREF S(0:2) MULT0 VTT_PG# PCI_STP# PLL2 PD# WD Logic SDATA SCLK VDDA I2C Logic 66B[0:2]/3V66[2:4] Power Up Logic 66IN/3V66-5 /2 Pin Configuration REF VDD XIN XOUT...