16/32-bit ARM microcontroller with external memory interface
• Each high-speed UART has 64 byte Receive and Transmit FIFOs.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, 16 B, 32 B, and 48 B.
• Transmitter FIFO trigger points at 0 B, 4 B, and 8 B.
• Each high-speed UART has an internal baud rate generator.
• The high-speed UARTs are designed to support data rates of (2400, 4800, 9600,
19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s.
• Each UART includes an internal loopback mode.
6.14 I2C-bus serial I/O controller
There are two I2C-bus interfaces in the LPC3180. The blocks for the I2C-bus are a master
only implementation supporting the 400 kHz I2C-bus mode and lower rates, with 7-bit
slave addressing. Each has a four word FIFO for both transmit and receive. An interrupt
signal is available from each block.
• The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in
Single Master mode only.
• Programmable clock to allow adjustment of I2C-bus transfer rates.
• Bidirectional data transfer.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
6.15 SPI serial I/O controller
The LPC3180 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial
interface that is able to interface with a large range of serial peripheral or memory devices
(SPI mode 0 to 3 compatible slave devices).
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3180 does not support operation as a slave.
• Supports slaves compatible with SPI modes 0 to 3.
• Half duplex synchronous transfers.
• DMA support for data transmit and receive.
• 1-bit to 16-bit word length.
• Choice of LSB or MSB ﬁrst data transmission.
• 64 × 16-bit input or output FIFO.
• Bit rates up to 52 Mbit/s.
Preliminary data sheet
Rev. 02 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
21 of 36