Document
NB6L611
2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
Multi−Level Inputs with Internal Termination
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Description The NB6L611 is a differential 1:2 clock or data fanout buffer. The
differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels.
The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L611 is a member of the ECLinPS MAX™ family of high performance clock and data management products.
Features
• Input Clock Frequency > 4.0 GHz • 280 ps Typical Propagation Delay • 100 ps Typical Rise and Fall Times • 0.5 ps maximum RMS Clock Jitter • Differential LVPECL Outputs, 780 mV Amplitude, typical • LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V • NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V • Internal Input Termination Resistors, 50 W • VREFAC Reference Output Voltage • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature • These are Pb−Free Devices
MARKING
DIAGRAM*
16 1
QFN−16
MN SUFFIX
1
CASE 485G
NB6L 611 ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to Application Note AND8002/D.
Q0
VTD
Q0
D
D
Q1
VTD
Q1
VREFAC
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
August, 2009 − Rev. 4
Publication Order Number: NB6L611/D
NB6L611
VCC VEE VEE VCC Exposed Pad (EP) 16 15 14 13
VTD 1 D2 D3
VTD 4
NB6L611
12 Q0 11 Q0 10 Q1 9 Q1
5678 VCC VREFAC VEE VCC
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1
VTD
−
Internal 50 W Termination Pin for D input.
2
D
ECL, CML,
Noninverted Differential Input. Note1. Internal 50 W Resistor to Termination Pin, VTD.
LVCMOS, LVDS,
LVTTL Input
3
D
ECL, CML,
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
LVCMOS, LVDS,
LVTTL Input
4
VTD
−
Internal 50 W Termination Pin for D input.
5
VCC
−
Positive Supply Voltage
6
VREFAC
Output Reference Voltage for direct or capacitor coupled inputs
7
VEE
−
Negative Supply Voltage
8
VCC
−
Positive Supply Voltage
9
Q1
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
10
Q1
LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
11
Q0
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
12
Q0
LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V.
13
VCC
−
Positive Supply Voltage
14
VEE
−
Negative Supply Voltage
15
VEE
−
Negative Supply Voltage
16
VCC
−
Positive Supply Voltage
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation.
2. All VCC and VEE pins must be externally connected to a power supply for proper operation.
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NB6L611
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model Machine Model
Moisture Sensitivity
16−QFN
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Value > 2 kV > 200V
Level 1 UL 94 V−0 @ 0.125 in
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC VEE VIO
VINPP IIN
Positive Power Supply Negative Power Supply Positive Input/Output Voltage Negative Input/Output Voltage
Differential Input Voltage |D − D| Input Current Through RT (50 W Resistor)
VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V
Static Surge
4.0
V
−4.0
V
−0.5 v VIo v VCC + 0.5
4..