Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
Description
3.3 V, 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
NB4N11M
Description The NB4N11M is a differential 1−to−2 clock/data
distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device produces two iden...
