Document
www.DataSheet4U.com
82C836 CHIPSet
Single-Chip 386sx AT Data Sheet
March 1993
P
R
E
L
I
M
I
N
A
R
Y
®
Copyright Notice
Software Copyright © 1993, Chips and Technologies, Inc. Manual Copyright © 1993, Chips and Technologies, Inc. All Rights Reserved. Printed in U.S.A.
Trademark Acknowledgment
CHIPS ® and CHIPS logotype are registered trademarks of Chips and Technologies, Inc. NEAT ™, NEATsx ™, SCAT ™, and SCATsx ™ are trademarks of Chips and Technologies, Inc. IBM®, IBM PC ®, IBM PC/AT ®, PS2 ™, and Microchannel ™ are trademarks of Intermational Business Machines Corporation. Intel ®, 386 ™, 387 ™, are trademarks of Intel Corporation. Lotus ® is a registered trademark of Lotus Development Corporation. MS-DOS ® is a registered trademark of Microsoft Corporation. Motorola ® is a registered trademark of Motorola.
Disclaimer
This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcr ibe, store in a retrieval system, or translate into any language or computer language, in any form or by any means , electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without express written permission of Chips and Technologies, Inc. The information contained in this document is being issued in advance of the production cycle for th The parameters for the device(s) may change before final production. e device(s).
Chips and Technologies, Inc. makes no representations or warranties regarding the contents of this m anual. We reserve the right to revise the manual or make changes in the specifications of the product describe d within it at any time without notice and without obligation to notify any person of such revision or changes. The information contained in this manual is provided for general use by our customers. Our customer s should be aware that the personal computer field is the subject of many patents. Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or a ssist others to infringe upon such rights.
Restricted Rights and Limitations
Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagra ph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.277-7013 Chips and Technologies, Inc. 2950 Zanker Road San Jose, California 95134 Phone: 408-434-0600
Contents
Section 1
82C836 CHIPSet Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2
Section 2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-9
Section 3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Backup and Power-Up/Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Power Management and Laptop Support . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-1 3-1 3-3 3-5 3-5 3-6
Section 4
Clock/Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Reset and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Control Arbitration and Basic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-2 4-3
Section 5
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM/Shadow RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCATsx Memory Address Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCATsx Memory Bank Utilization . . . . . . . . . . . . . . . . . . . . . . ..