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TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
.EATURES:
• • • • • • • • •
IDT728981
128 x 128 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS®) 4 RX inputs—32 channels at 64 Kbit/s per serial line 4 TX output—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 5V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40°C to +85°C
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream.
.UNCTIONAL DESCRIPTION
A functional block diagram of the IDT728981 device is shown below. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four output (TX0-3) serial streams are provided in the IDT728981 device allowing a complete 128 x 128 channel non-blocking switch matrix to be constructed. The serial interface (C4i) clock for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 128-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed.
DESCRIPTION:
The IDT728981 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT728981 can handle as many as 128, 64 Kbit/s input and output channels. Those 128 channels are divided into 4 serial inputs and
.UNCTIONAL BLOCK DIAGRAM
C4i
F0i
VCC
GND
ODE
Timing Unit
RX0 RX1 RX2 RX3
Output MUX
TX0
Receive Serial Data Streams
Data Memory Control Register Connection Memory
Transmit Serial Data Streams
TX1 TX2 TX3
Microprocessor Interface
5703 drw01
DS CS R/W A0/ DTA D0/ A5 D7
JANUARY 2001
1
2001 Integrated Device Technology, Inc. DSC-5703/1
IDT728981 Time Slot Interchange Digital Switch 128 x 128
Commercial Temperature Range
PIN CON.IGURATION
DTA DNC(1)
DNC(1)
DNC(1)
DNC(1)
DNC(1)
ODE
RX1
DTA
RX2
RX0
ODE TX0
RX0
RX1
TX0
TX1
TX2
INDEX
INDEX
44
41
39
43
42
38
40
37
36
2
35
44
43
42
41
RX3 VCC VCC VCC VCC VCC F0i C4i A0 A1 A2
1
40
7 8 9 10 11 12 13 14 15 16 17
21 20 22
39 38 37 36 35 34 33 32 31 30 29
TX3 DNC(1) DNC(1) DNC(1) DNC(1) GND D0 D1 D2 D3 D4
RX3 VCC VCC VCC VCC VCC F0i C4i A0 A1 A2
34
6
4
5
3
DNC(1)
RX2
TX1
TX2
1 2 3 4 5 6 7 8 9 10 11
12 15 17 13 14 18 16 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
TX3 DNC(1) DNC(1) DNC(1) DNC(1) GND D0 D1 D2 D3 D4
23
24
25
26
18
19
27
28
DTA
5703 drw02
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
5703 drw04
DNC(1)
CS D7 D6 DNC(1) DS R/W D5 A3 A4 A5 DNC(1)
5703 drw03
DNC(1)
DNC(1)
D7
D6
DS
R/W
CS
D5
A3
A4
A5
RX0 RX1 RX2
ODE TX0 TX1 TX2 TX3 DNC(1) DNC(1) DNC(1) DNC(1) GND D0 D1 D2 D3 D4 D5 D6 D7 CS
PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44-1, order code: J) TOP VIEW
RX3 VCC VCC VCC VCC VCC F0i C4i A0 A1 A2
PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW
NOTE: 1. DNC - Do Not Connect
A3 A4 A5 DS R/W
PIN DESCRIPTIONS
SYMBOL
GND VCC
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in. (P40-1, order code: P) TOP VIEW
NAME
Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 3 Frame Pulse Clock Address 0 to 5 Data Strobe Read/Write Chip Select Data Bus 0 to 7 TX Outputs 0 to 3 (Three-state Outputs) Output Drive Enable
I/O
DESCRIPTION
Ground Rail. +5.0 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS® specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT728981 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control.
2
DTA
RX0-3
O I I I I I I I I/O O I
F0i C4i
A0-A5 DS R/W
CS
D0-D7 .