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TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
.EATURES:
• • • • • • • • •
IDT728980
256 x 256 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS®) 8 RX inputs—32 channels at 64 Kbit/s per serial line 8 TX output—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 5V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40°C to +85°C
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream.
.UNCTIONAL DESCRIPTION
A functional block diagram of the IDT728980 device is shown on below. The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT728980 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is 16 bits wide and
DESCRIPTION:
The IDT728980 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT728980 can handle as many as 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs and
.UNCTIONAL BLOCK DIAGRAM
C4i
F0i
VCC
GND
ODE
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7
Timing Unit
TX0
Output MUX Transmit Serial Data Streams
TX1 TX2
Receive Serial Data Streams
Data Memory Control Register Connection Memory
TX3 TX4 TX5 TX6 TX7
Microprocessor Interface
5706 drw01
DS CS R/W A0/ DTA D0/ A5 D7
CCO
JANUARY 2001
1
2001 Integrated Device Technology, Inc. DSC-5706/1
IDT728980 Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
PIN CON.IGURATION
DNC(1) DNC(1) CCO
DNC(1) DTA CCO
RX1
DTA
RX2
RX0
ODE TX0
RX0
TX0
TX1
TX2
INDEX
6
4
5
3
2
44
43
42
41
40
44
41
39
43
42
38
37
36
35
TX2
INDEX
RX1
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
1
7 8 9 10 11 12 13 14 15 16 17
21 20 22
39 38 37 36 35 34 33 32 31 30 29
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
40
34
DNC(1)
ODE
RX2
TX1
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
DTA RX0 RX1 RX2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
5706 drw04
CCO ODE TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4 D5 D6 D7 CS
12
15
17
13
14
18
16
19
20
21
23
24
25
26
18
19
27
28
22
5706 drw03
DNC(1)
DNC(1)
CS D7
D6
DNC(1)
R/W
DS R/W
D7
D6
DS
CS
D5
A3
A4
A5
D5
A3
A4
A5
5706 drw02
RX4 RX5
PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44-1, order code: J) TOP VIEW
RX6 RX7 VCC F0i C4i A0 A1 A2 A3 A4
PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW
NOTE: 1. DNC - Do Not Connect.
A5 DS R/W
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in. (P40-1, order code: P) TOP VIEW
PIN DESCRIPTIONS
SYMBOL
GND VCC
NAME
Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 7 Frame Pulse Clock Address 0 to 5 Data Strobe Read/Write Chip Select Data Bus 0 to 7 TX Outputs 0 to 7 (Three-state Outputs) Output Drive Enable Control Channel Output
I/O
DESCRIPTION
Ground Rail. +5.0 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS® specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT728980 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 a.