IDT74SSTU32864

www.DataSheet4U.com IDT74SSTU32864/A 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O COMMERCIAL TEMPERATURE RANGE 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O IDT74SSTU32864/A FEATURES: 1:1 and 1:2 registered buffer 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) Available in 96-pin LFBGA package APPLICATIONS: Ideally suited for DDR2 DIMM registered applications SSTU32864 is optimized for DDR2 Raw Cards B and C R-DIMMs SSTU32864A is optimized for DDR2 Raw Card A R-DIMMs Along with CSPU877, zero delay PLL clock buffer, provides complete solution for DDR2 DIMMs The SSTU32864/A is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864/A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from the A configuration (when low) to B configuration (when high). The C1 input controls the configuration from the 25-bit 1:1 (when l...