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QR0001 Dataheets PDF



Part Number QR0001
Manufacturers National Semiconductor
Logo National Semiconductor
Description QuickRing Data Stream Controller
Datasheet QR0001 DatasheetQR0001 Datasheet (PDF)

www.DataSheet4U.com QR0001 QuickRing Data Stream Controller PRELIMINARY October 1994 QR0001 QuickRing TM Data Stream Controller General Description QuickRing is a point-to-point data transfer architecture designed to facilitate high speed data streams The QuickRing architecture can be applied both inside the chassis as well as outside the chassis environments to increase data throughput Each QR0001 QuickRing Controller node in the ring is capable of streaming up to 231 MSamples s per signal l.

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www.DataSheet4U.com QR0001 QuickRing Data Stream Controller PRELIMINARY October 1994 QR0001 QuickRing TM Data Stream Controller General Description QuickRing is a point-to-point data transfer architecture designed to facilitate high speed data streams The QuickRing architecture can be applied both inside the chassis as well as outside the chassis environments to increase data throughput Each QR0001 QuickRing Controller node in the ring is capable of streaming up to 231 MSamples s per signal line simultaneously including protocol overhead This device is intended for use in applications that handle highbandwidth data streams associated with graphics uncompressed video disk arrays high-speed local area networks multiprocessor systems and to interconnect peripherals over a few meters of cable The QR0001 QuickRing Controller can be used to augment the performance of traditional backplane buses in personal computers workstations and high-end systems The QR0001 is useful for routing high-bandwidth streams in systems that are larger or topologically more complex than bus-based systems Features Y Y Y Y Y 160-pin PQFP package 16 node single ring capability Peak theoretical rate over 1 GByte sec for 16 node ring Support for Multi-Ring topologies Error detection detects 1- and 2-bit errors RING INTERFACE Y Precision PLL captures data at 231 MSamples s max Y 33 MHz maximum ring clock frequency Y Low Voltage Differential Signaling (LVDS) ring interface (IEEE P1596 3) CLIENT INTERFACE Y 132 MBytes s data transfer rate at both Tx and Rx ports Y 32-bit transmit and receive data ports Y Readable internal diagnostic register Y TTL signal interface Block Diagram TL F 11928 – 1 QuickRingTM is a trademark of Apple Computer Incorporated C1995 National Semiconductor Corporation TL F 11928 RRD-B30M75 Printed in U S A Table of Contents 10 20 30 31 32 33 34 35 SIGNAL DESCRIPTION BASIC STRUCTURE CLIENT INTERFACE Type and Symbol Fields at the Client Ports Client Transmit Port Transmit Port Timing Relationships Client Receive Port Receive Port Timing Relationships 3 5 1 Client Receive Port Interface Recommendations (PIPE asserted) 36 37 38 39 Client Interface Field Definitions Client Type Fields Transmit Port Head Fields Receive Port Head Fields 4 10 Head Symbol on the Ring 4 11 Payload Symbols on the Ring 4 12 Tail Symbol on the Ring 4 13 Access Symbols on the Ring 4 14 Summary of Ring Port Field Format 5 0 CLOCK SIGNALS 6 0 ABORT SIGNAL 7 0 BRIDGES 8 0 LITTLE BIG ENDIAN ISSUES 9 0 RESET AND INITIALLZATION 9 1 Reset 9 2 Node 0 Selection and Initialization 9 3 Node ID Assignment 9 4 Sequence for Node 0 9 5 Sequence for All Qther Nodes on Ring 10 0 QR0001 OPERATION FLOW 10 1 Ring Traffic Flow Priorities for DnSS port Transmissions 10 2 Inside the Source Node (Device Transmitting Data) 10 3 Summary of Source Node Actions 40 41 42 43 44 45 46 47 48 49 RING INTERFACE Type and Symbol Field at the Ring Ports Data and Frames Symbol Flux on Ring Data on the Ring (Head Payload Tail) Access on the Ring (Voucher Ticket Abort Null) Mapping of Type Frame Data and EDC Code on the Ring Ring Interface Field Definitions Routing Symbols are Common to All Ports Ring Type Fields 13 0 DC ELECTRICAL CHARACTERISTICS 14 0 AC TIMING PARAMETERS 15 0 CONNECTION DIAGRAM 16 0 GLOSSARY 17 0 REVISION NOTES 11 0 BOARD CONSIDERATIONS 11 1 Upstream Port Signal Termination 11 2 QuickRing Physical Layer Details 12 0 POWER AND DECOUPLING ISSUES 12 1 Power Issues 12 2 Decoupling Issues 10 4 Inside the Target Node 10 5 Summary of Target Node Actions 3 10 Payload Symbols at the Rx and Tx Ports 3 11 Null Symbols at the Rx and Tx Ports 3 12 The HOP fields and the Uniqueness of Symbol Streams 3 13 Summary of Client Port Field Format 3 14 Readable Registers 3 15 Error Detection 2 1 0 Signal Description Pin Name RESET ABORT PIPE I O I O I No 1 1 1 Description RESET When this input is released the initialization sequence begins ABORT When asserted it indicates that a failure was detected ABORT is negated by asserting Reset PIPE When PIPE is negated (non-pipelined timing) at the Client ports both the symbol and type fields correspond to each other during the same clock cycle When PIPE is asserted (pipelined timing) the timing of the Type field leads by one clock at the receive port and trails by one clock at the transmit port (The type and symbol fields are pipelined ) NODE0 When asserted the controller is configured as having Node ID 0 Node 0 is responsible for governing the initialization process in the ring RING CLOCK This clock input is the time-base for the ring interface A clock input should be present when the CKSRC pin is asserted When CKSRC is negated RGCLK should be tied low CLOCK SOURCE Designates the source of the ring clock When asserted RGCLK is the clock source used for the Ring interface When this pin is negated the clock is derived from the differential UpCLK CLOCK OUT If CKSRC is asserted then CLKOUT is frequency-locked to the RGCLK If CKSRC is nega.


PT122xx QR0001 RG1A


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