ECL-INTERFACED PROGRAMMABLE DELAY LINE
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PDU108H
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU108H)
FEATURES
• • • • • Digitall...
Description
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PDU108H
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU108H)
FEATURES
Digitally programmable in 8 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 10KH-ECL interfaced & buffered Fits standard 16-pin DIP socket
GND ENB 1 2 16 15
data 3 ® delay devices, inc.
PACKAGES
GND OUT
IN A0 VEE
6 7 8 10 9 A1 A2
GND ENB N/C N/C N/C IN A0 VEE
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GND OUT N/C N/C N/C N/C A1 A2
PDU108H-xx DIP PDU108H-xxM Military DIP
PDU108H-xxC3 SMD PDU108H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU108H-series device is a 3-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A2-A0) according to the following formula: TDA = TD0 + TINC * A
PIN DESCRIPTIONS
IN OUT A2 A1 A0 ENB VEE GND Signal Input Signal Output Address Bit 2 Address Bit 1 Address Bit 0 Output Enable -5 Volts Ground
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 5% or ...
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