Monolithic serial interface compiler encoder
BL1302A57/S
General Description
The BL1302A57/S is an A-law monolithic PCM Pin Assignment
CODEC/filter which has the ...
Description
BL1302A57/S
General Description
The BL1302A57/S is an A-law monolithic PCM Pin Assignment
CODEC/filter which has the A/D and D/A
conversion and a serial PCM interface. The device is fabricated using the advanced double-poly nwell CMOS process. It is pin compatible with TP3057. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a
VBB GNDA VFRO
VCC FSR
DR BCLKR/CLKSEL
MCLKR/PDN
1 2 3 4 5 6 7 8
BL1302A57
16 VFXI+ 15 VFXI14 GSX 13 TSX 12 FS X 11 DX 10 BCLKX 9 MCLKX
companding coder which samples the filtered signal
and encodes it in the companded A-law PCM format.
The decode portion consists of an expanding
decoder, which reconstructs the
Analog signal from the companded A-law code, a low-pass filter which corrects for the sinx/x
response of the decoder output and rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads. The device requires two 1.536 MHz,
1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous;
transmit and receive bit clocks , which may vary from 64 KHz to 2.048 MHz; and transmit and
receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with
both industry standard formats.
.
Features...
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