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M366S1623ET0 Dataheets PDF



Part Number M366S1623ET0
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description Synchronous DRAMs
Datasheet M366S1623ET0 DatasheetM366S1623ET0 Datasheet (PDF)

www.DataSheet4U.com M366S1623ET0 Revision History Revision 0.0 (Dec, 2000) • PC133 first published. PC133 Unbuffered DIMM REV. 0.0 Dec, 2000 M366S1623ET0 M366S1623ET0 SDRAM DIMM PC133 Unbuffered DIMM 16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M366S1623ET0 is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S1623ET0 consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in .

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www.DataSheet4U.com M366S1623ET0 Revision History Revision 0.0 (Dec, 2000) • PC133 first published. PC133 Unbuffered DIMM REV. 0.0 Dec, 2000 M366S1623ET0 M366S1623ET0 SDRAM DIMM PC133 Unbuffered DIMM 16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M366S1623ET0 is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S1623ET0 consists of sixteen CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S1623ET0 is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE • Performance range Part No. Max Freq. (Speed) M366S1623ET0-C75 PC133@CL3 & PC100@CL3 Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM PCB : Height (1,375mil), double sided component • • • • • • • • PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 *A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 72 44 DU 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 52 *CB2 80 53 *CB3 81 82 54 VSS 55 DQ16 83 56 DQ17 84 PIN NAMES Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK3 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Don′t use No connection CKE0 ~ CKE1 Clock enable input * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 0.0 Dec, 2000 M366S1623ET0 PIN CONFIGURATION DESCRIPTION Pin CLK CS Name System clock Chip select PC133 Unbuffered DIMM Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the c.


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