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IDT723652 Dataheets PDF



Part Number IDT723652
Manufacturers IDT
Logo IDT
Description (IDT7236x2) CMOS SyncBiFIFO
Datasheet IDT723652 DatasheetIDT723652 Datasheet (PDF)

www.DataSheet4U.com CMOS SyncBiFIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 IDT723652 IDT723662 IDT723672 FEATURES • • • • • • • • • • • Memory storage capacity: IDT723652 – 2,048 x 36 x 2 IDT723662 – 4,096 x 36 x 2 IDT723672 – 8,192 x 36 x 2 Supports clock frequencies up to 83MHz Fast access times of 8ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering.

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www.DataSheet4U.com CMOS SyncBiFIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 IDT723652 IDT723662 IDT723672 FEATURES • • • • • • • • • • • Memory storage capacity: IDT723652 – 2,048 x 36 x 2 IDT723662 – 4,096 x 36 x 2 IDT723672 – 8,192 x 36 x 2 Supports clock frequencies up to 83MHz Fast access times of 8ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB • • • Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving 120-pin Thin Quad Flatpack (TQFP) Pin compatible to the lower density parts, IDT723622/723632/723642 Industrial temperature range (–40° C to +85°C) is available DESCRIPTION The IDT723652/723662/723672 is a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 83MHz and have read access times as fast as 8ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. FUNCTIONAL BLOCK DIAGRAM MBF1 CLKA CSA W/RA ENA MBA Mail 1 Register Input Register Output Register Port-A Control Logic RST1 FIFO1, Mail1 Reset Logic 36 RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 36 Write Pointer Read Pointer EFB/ORB AEB FFA/IRA AFA FIFO 1 Status Flag Logic FS0 FS1 A0 - A35 13 Programmable Flag Offset Registers FIFO 2 Timing Mode FWFT B0 - B35 EFA/ORA AEA Status Flag Logic Write Pointer RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Mail 2 Register 36 FFB/IRB AFB 36 Read Pointer Output Register FIFO2, Mail2 Reset Logic Input Register RST2 Port-B Control Logic CLKB CSB W/RB ENB MBB 5609 drw 01 MBF2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 DSC-5609/4 IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through PIN CONFIGURATION NC NC VCC CLKB ENB W/RB CSB GND FFB/IRB EFB/ORB AFB AEB VCC MBF1 MBB RST2 FS1 GND FS0 RST1 MBA MBF2 AEA AFA VCC EFA/ORA FFA/IRA CSA W/RA ENA CLKA GND NC NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC NC A35 A34 A33 .


IDCS-7328 IDT723652 IDT723662


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