Pentium/ProTM System and Cyrix™ Clock Chip
The ICS9148-25 is a Clock Synthesizer chip for Pentium and
PentiumPro plus Cyrix CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
Features include four CPU, seven PCI and eight SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency, plus the IOAPIC output powered by VDDL.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The ICS9148-25 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V supply.
Sperad Spectrum is modulated in center-spread mode on CPU/
SDRAM/PCI clocks. Modulation amount is selectable at
power-up (latched inputs) for ±0.5, ±1.0, ±2.0 or No spreading.
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.318 MHz ), USB, Plus Super I/O
• Spread spectrum for CPU/SDRAM/PCI clocks default
• Supports single or dual processor systems
• Modulation of Spread Spectrum selectable as ±0.5, ±1.0,
±2.0 or none
• Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3
and 68MHz (Turbo of 66.6) speeds.
• Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on PCI clocks
• CPU clocks to PCI clocks skew 1-4ns (CPU early)
• MODE input pin selects optional power management
input control pins
• Two fixed outputs, 48MHz and 24 MHz
• Separate 2.5V and 3.3V supply pins
- 2.5V or 3.3V output: CPU, IOAPIC (Strength
- 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
• No power supply sequence requirements
• 48 pin 300 mil SSOP
Pentium is a trademark on Intel Corporation.
9148-25 Rev B 5/20/99
VDD = Supply for PLL core.
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#,
VDD4 = 48MHz, 24MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.