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CY7B995 Dataheets PDF



Part Number CY7B995
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description High-Speed Multi-Phase PLL Clock Buffer
Datasheet CY7B995 DatasheetCY7B995 Datasheet (PDF)

www.DataSheet4U.com CY7B995 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer Features • 2.5V or 3.3V operation • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 100 ps • Cycle-cycle jitter <100 ps • ± 2% max output duty cycle • Selectable output drive strength • Selectable positive or negative edge synchronization • Eight LVTTL outputs driving 50Ω terminated lines • LVCMOS/LVTTL over-voltage tolerant reference input • Selectable phase-.

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www.DataSheet4U.com CY7B995 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer Features • 2.5V or 3.3V operation • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 100 ps • Cycle-cycle jitter <100 ps • ± 2% max output duty cycle • Selectable output drive strength • Selectable positive or negative edge synchronization • Eight LVTTL outputs driving 50Ω terminated lines • LVCMOS/LVTTL over-voltage tolerant reference input • Selectable phase-locked loop (PLL) frequency range and lock indicator • Phase adjustments in 625/1250 ps steps up to ± 7.5 ns • (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios • Spread-Spectrum-compatible • Power-down mode • Selectable reference divider • Industrial temperature range: -40°C to +85°C • 44-pin TQFP package Description The CY7B995 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems. The user can program both the frequency and the phase of the output banks through nF[0:1] and DS[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA (3.3V). Block Diagram TEST PE/HD PD#/DIV REF 3 Pin Configuration FS VDDQ1 FS VDD REF VSS TES T 2F1 2F0 VDD VDDQ1 4F0 3F1 3F0 /R /N 3 3 3 3 3 PLL FB DS1:0 1F1:0 3 3 Phase Select LOCK 1Q0 1Q1 3 2Q0 Phase Select 2F1:0 3 2Q1 3F1:0 3 3 Phase Select and /K 3Q0 3Q1 VDDQ3 4F1 1 sOE# 2 PD#/DIV 3 PE/HD 4 VDDQ4 5 VDDQ4 6 4Q1 7 4Q0 8 VSS 9 VSS 10 VSS 11 44 43 42 41 40 39 38 37 36 35 34 CY7B995 12 13 14 15 16 17 18 19 20 21 22 3Q1 3Q0 VDDQ3 VDDQ3 FB 2Q1 2Q0 VSS VSS 4F1:0 3 3 Phase Select and /M 4Q0 4Q1 VDDQ4 sOE# Cypress Semiconductor Corporation Document #: 38-07337 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 24, 2004 1F1 33 1F0 32 DS1 31 DS0 30 LOCK 29 VDDQ1 28 VDDQ1 27 1Q0 26 1Q1 25 VSS 24 VSS 23 VSS CY7B995 Pin Description Pin 39 17 37 Name REF FB TEST I/O[1] I I I Type LVTTL/LVCMOS LVTTL 3-Level Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops c.



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