Document
www.DataSheet4U.com
LMX2330U/LMX2331U/LMX2332U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
July 2002
LMX2330U/LMX2331U/LMX2332U PLLatinum™ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2330U 2.5 GHz/600 MHz LMX2331U 2.0 GHz/600 MHz LMX2332U 1.2 GHz/600 MHz
General Description
The LMX233xU devices are high performance frequency synthesizers with integrated dual modulus prescalers. The LMX233xU devices are designed for use as RF and IF local oscillators for dual conversion radio transceivers. A 32/33 or a 64/65 prescale ratio can be selected for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a 128/129 prescale ratio can be selected for both the LMX2331U and LMX2332U RF synthesizers. The IF circuitry contains an 8/9 or a 16/17 prescaler. Using a proprietary digital phase locked loop technique, the LMX233xU devices generate very stable, low noise control signals for RF and IF voltage controlled oscillators. Both the RF and IF synthesizers include a two-level programmable charge pump. The RF synthesizer has dedicated Fastlock circuitry. Serial data is transferred to the devices via a three-wire interface (Data, LE, Clock). Supply voltages from 2.7V to 5.5V are supported. The LMX233xU family features ultra low current consumption: LMX2330U (2.5 GHz) — 3.3 mA, LMX2331U (2.0 GHz) — 2.9 mA, LMX2332U (1.2 GHz) — 2.5 mA at 3.0V. The LMX233xU devices are available in 20-Pin TSSOP and 24-Pin CSP surface mount plastic packages.
Features
n n n n Ultra Low Current Consumption Upgrade and Compatible to LMX233xL Family 2.7V to 5.5V Operation Selectable Synchronous or Asynchronous Powerdown Mode: ICC-PWDN = 1 µA typical Selectable Dual Modulus Prescaler: LMX2330U RF: 32/33 or 64/65 LMX2331U RF: 64/65 or 128/129 LMX2332U RF: 64/65 or 128/129 LMX2330U/31U/32U IF: 8/9 or 16/17 Selectable Charge Pump TRI-STATE ® Mode Programmable Charge Pump Current Levels RF and IF: 0.95 or 3.8 mA Selectable Fastlock™ Mode for the RF Synthesizer Push-Pull Analog Lock Detect Output Available in 20-Pin TSSOP and 24-Pin Chip Scale Package (CSP)
n
n n n n n
Applications
n Mobile Handsets (GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS) n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners
Thin Shrink Small Outline Package (MTC20)
Chip Scale Package (SLB24A)
10136680 10136681
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS101366
www.national.com
LMX2330U/LMX2331U/LMX2332U
Functional Block Diagram
10136601
www.national.com
2
LMX2330U/LMX2331U/LMX2332U
Connection Diagrams
Chip Scale Package (SLB) (Top View) Thin Shrink Small Outline Package (TM) (Top View)
10136602
10136639
Pin Descriptions
Pin Name VCC Pin No. 24-Pin CSP 24 Pin No. 20-Pin TSSOP 1 I/O — Description Power supply bias for the RF PLL analog and digital circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. RF PLL charge pump power supply. Must be ≥ VCC. RF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. Ground for the RF PLL digital circuitry. RF PLL prescaler input. Small signal input from the VCO. RF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU RF PLL can be driven differentially when the bypass capacitor is omitted. Ground for the RF PLL analog circuitry. Reference oscillator input. The input has an approximate VCC/2 threshold and can be driven from an external CMOS or TTL logic gate. Ground for the IF PLL digital circuits, MICROWIRE™, FoLD, and oscillator circuits. Programmable multiplexed output pin. Functions as a general purpose CMOS TRI-STATE output, RF/IF PLL push-pull analog lock detect output, N and R divider output or Fastlock output, which connects a parallel resistor to the external loop filter. MICROWIRE Clock input. High impedance CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock. MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB of Data is shifted in first. The last two bits are the control bits. MICROWIRE Latch Enable input. High impedance CMOS input. When LE transitions HIGH, Data stored in the shift register is loaded into one of 4 internal control registers. Ground for the IF PLL analog circuitry.
VP RF Do RF GND fIN RF fIN RF
2 3 4 5 6
2 3 4 5 6
— O — I I
GND OSCin GND FoLD
7 8 10 11
7 8 9 10
— I — O
Clock Data LE
12 14 15
11 12 13
I I I
GND
16
14
—
3
www.national.com
LMX2330U/LMX2331U/LMX2332U
Pin Descriptions
Pin Name fIN IF Pin No. 24-Pin CSP 17
(Continued) Pin No. 20-Pin TSSOP 15 I/O I Description IF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU IF PLL can be driven differentially when the bypass capacitor is omitted. IF PLL pre.