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74AUP1G332 Dataheets PDF



Part Number 74AUP1G332
Manufacturers NXP
Logo NXP
Description Low Power 3-Input OR Gate
Datasheet 74AUP1G332 Datasheet74AUP1G332 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G332 Low-power 3-input OR gate Rev. 01 — 13 November 2006 Product data sheet 1. General description The 74AUP1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entir.

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www.DataSheet4U.com 74AUP1G332 Low-power 3-input OR gate Rev. 01 — 13 November 2006 Product data sheet 1. General description The 74AUP1G332 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G332 provides a single 3-input OR gate. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 4000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C www.DataSheet4U.com NXP Semiconductors 74AUP1G332 Low-power 3-input OR gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G332GW 74AUP1G332GM 74AUP1G332GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code aG aG aG Type number 74AUP1G332GW 74AUP1G332GM 74AUP1G332GF 5. Functional diagram 3 1 6 B A C 001aad933 Y 4 1 3 6 1 4 001aad934 Fig 1. Logic symbol Fig 2. IEC logic symbol B A C 001aad935 Y Fig 3. Logic diagram 74AUP1G332_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 13 November 2006 2 of 16 www.DataSheet4U.com NXP Semiconductors 74AUP1G332 Low-power 3-input OR gate 6. Pinning information 6.1 Pinning 74AUP1G332 74AUP1G332 A GND 1 2 6 5 C GND VCC B B 3 001aad930 A 1 6 C A GND 74AUP1G332 1 2 3 6 5 4 C VCC Y 2 5 VCC 3 4 Y B 4 Y 001aad931 001aad932 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol A GND B Y VCC C Pin description Pin 1 2 3 4 5 6 Description data input A ground .


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