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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
1
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Overview
The VRS550 and the VRS560 are both low cost 8-bit microcontrollers based on the standard 80C51 microcontroller family architecture. They are pin-to-pin compatible and drop-in replacements for most 8051 MCUs. The VRS550 and VRS560 have 8kB and 16kB, respectively of Flash memory. Both devices have 256 bytes of RAM memory. The hardware features of these devices and their reprogrammability make them suitable for a wide range of applications. These VRS550 and VRS560 are both available in PLCC-44 and QFP-44 packages in the Industrial temperature range. The Flash memory can be programmed using programmers available from Goal Semiconductor or other 3rd party commercial programmers.
FIGURE 1: VRS550 / VRS560 FUNCTIONAL DIAGRAM
Feature Set
• • • • • • • • • • • • • • • • • • •
General 80C51/80C52 pin compatible 12 clock periods per machine cycle 8k / 16k on-chip Flash memory 256 Bytes on-chip data RAM 32 I/O lines on four 8-bit ports Full duplex serial port (UART) 3, 16-bit Timers/Counters Watch Dog Timer 8-bit Unsigned Division / Multiply BCD arithmetic Direct and Indirect Addressing Two levels of interrupt priority and nested interrupts Power saving modes Code protection function Operates at a clock frequency of up to 25MHz Low EMI (inhibit ALE) Programming voltage: 12V Industrial Temperature range (-40° C to +85° C) 5V and 3V versions available (see Ordering information.)
FIGURE 2: VRS550 / VRS560 PLCC AND QFP PINOUT DIAGRAMS
T2EX/P1.1
P0.0/AD0
P0.2/AD2
P0.1/AD1
T2/P1.0
8051 PROCESSOR 8k / 16k FLASH 256 bytes of RAM
ADDRESS/ DATA BUS
P1.5 P1.6 P1.7 RESET RXD/P3.0 NC TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5
7
6
VDD
1
P0.3/AD3
40
P1.4
P1.2
P1.3
NC
39
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA NC ALE #PSEN P2.7/A15 P2.6/A14
PORT 0
8
PORT 1
8
VRS550 / VRS560 PLCC-44
UART
PORT 2
8
17 18
28
29
P2.5/A13
#RD/P3 .7
XTAL1
VSS
NC
2 INTERRUPT INPUTS TIMER 0 TIMER 1 TIMER 2 RESET POWER CONTROL WATCHDOG TIMER
PORT 3
8
#WR/P3.6
P0.5/AD5
P0.4/AD4
P0.6/AD6
P0.7/AD7
P2.2/A10
P2.7/A15
P2 .3/A11
P2.6/A14
P2 .4/A12
23 22
XTAL2
P2 .0/A8
P2 .1/A9
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD NC T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4
34
33
#PSEN
P2.5/A13
#EA
ALE
NC
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 NC VSS XTAL1 XTAL2
VRS550 / VRS560 QFP-44
44 1
12 11
#RD/P3.7 #WR/P3.6
NC
#INT0/P3.2
#INT1/P3.3
RXD/P3.0
TXD/P3.1
T0/P3.4 T1/P3.5
P1.5
P1.6
P1.7
RESET
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
2
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Pin Descriptions for QFP-44
TABLE 1: PIN DESCRIPTIONS FOR QFP-44/
QFP - 44
Name
I/O
Function
QFP - 44
Name
I/O
Function
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
P1.5 P1.6 P1.7 RES RXD P3.0 NC TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS NC P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13
I/O I/O I/O I I I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O O I/O O I/O O I/O O I/O O I/O O
Bit 5 of Port 1 Bit 6 of Port 1 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 No Connect Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground No Connect Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
P2.6 A14 P2.7 A15 #PSEN ALE NC #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD NC T2 P1.0 T2EX P1.1 P1.2 P1.3 P1.4
I/O O I/O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I/O I/O I/O
Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable No Connect External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Addres.