HY5DU56422BT-D43

www.DataSheet4U.com HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 256M-P DDR SDRAM HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Revision History 1. Revision 0.2 (Jan. 2003) 1) Changed VDDmin from 2.4V to 2.5V at Page22 2) Corrected some typos. 2. Revision 0.3 (Feb. 2003) 1) IDD value update at Page 23, 24. 2) Changed some AC Paramters on AC Characteristics Table at Page27, 28. 3. Revision 0.4 (Aug. 2003) 1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD) Rev. 0.4 / Aug. 2003 2 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU56422BT ,HY5DU56822BT are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output vo...