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CLC5955 Dataheets PDF



Part Number CLC5955
Manufacturers National Semiconductor
Logo National Semiconductor
Description Broadband Monolithic A/D Converter
Datasheet CLC5955 DatasheetCLC5955 Datasheet (PDF)

www.DataSheet4U.com April 2002 CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter N CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter General Description The CLC5955 is a monolithic 11-bit, 55MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5955 features differential analog input.

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www.DataSheet4U.com April 2002 CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter N CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter General Description The CLC5955 is a monolithic 11-bit, 55MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5955 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V or 2.5V) programmable output logic, and a proprietary multistage quantizer. The CLC5955 is fabricated on the ABIC-V 0.8 micron BiCMOS process. The CLC5955 features a 74dBc spurious free dynamic range (SFDR) and a 64dB signal to noise ratio (SNR). The wideband track-and-hold allows sampling of IF signals to greater than 250MHz. The part produces two-tone, dithered, SFDR of 83dBFS at 75MHz input frequency. The differential analog input provides excellent common mode rejection, while the differential universal clock inputs minimize jitter. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5955 operates from a single +5V power supply. Operation over the industrial temperature range of -40°C to +85°C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications. Features • 55MSPS • Wide dynamic range SFDR: 74dBc SFDR w/dither: 85dBFS SNR: 64dB • IF sampling capability • Input bandwidth = 0-300MHz • Low power dissipation: 640mW • Very small package: 48-pin TSSOP • Single +5V supply • Data valid clock output • Programmable output levels: 3.3V or 2.5V Applications • • • • • • • • Cellular base-stations Digital communications Infrared/CCD imaging IF sampling Electro-optics Instrumentation Medical imaging High definition video N MTD N ME79TG CLC5955 CLC5957 Actual Size ADC Block Diagram DAV Clock In IF Input IF Saw First IF Receiver DVGA (∆G = 42dB) CLC5903 CLC5955 11-bit 55MSPS ADC 11 DAV Dig. Tuner/ Filter AGC 20 ~ ~ BPF (150MHz typ.) Noise BPF 3-bit (Gain Control) AIn T/H Q Q Q Q Bit Align/Error Correct 11 ADC Out Decimation/filter = 190/0.8 Output BW = 50M/190 X 0.8 = 210KHz Single Tone Output Spectrum w/Dither 0 90 Receiver SINAD vs. Input Amplitude SINAD dBc (BW = 216KHz) 80 70 60 50 40 30 20 10 0 -125 -100 -75 -50 -25 0 -10 Fin = 25.3MHZ Fsample = 66MHz Output Level (dBFS) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 4 8 12 16 20 24 28 32 Frequency (MHz) © 2002 National Semiconductor Corporation Printed in the U.S.A. Input (dBFS) http://www.national.com CLC5955 Electrical Characteristics (Vcc= +5V, 55MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C) PARAMETERS CONDITIONS TEMP MIN RESOLUTION DIFF. INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE SNR SFDR DYNAMIC PERFORMANCE large-signal bandwidth overvoltage recovery time effective aperture delay (Ta) aperture jitter Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C RATINGS TYP 11 2.048 75 64 74 300 12 -0.41 0.3 MAX Bits V MSPS dBFS dBc MHz ns ns ps(rms) UNITS NOTES 2 1 1 1 1 fin = 25MHz, Ain = -1dBFS fin = 25MHz, Ain = -1dBFS Ain = -3dBFS Ain = 1.5FS (0.01%) 55 60 65 NOISE AND DISTORTION signal-to-noise ratio (w/o 50 harmonics) fin = 5.0MHz Ain = -1dBFS Ain = -1dBFS fin = 25MHz fin = 75MHz Ain = -3dBFS fin = 150MHz Ain = -15dBFS fin = 250MHz Ain = -15dBFS spurious-free dynamic range fin = 5.0MHz Ain = -1dBFS Ain = -1dBFS fin = 25MHz fin = 75MHz Ain = -3dBFS fin = 150MHz Ain = -15dBFS fin = 250MHz Ain = -15dBFS intermodulation distortion fin1 = 149.84MHz, fin2 = 149.7MHz Ain = -10dBFS fin1 = 249.86MHz, fin2 = 249.69MHz Ain = -10dBFS dithered performance spurious-free dynamic range Ain = -6dBFS fin = 19MHz intermodulation distortion Ain = -12dBFS fin1 = 74MHz, fin2 = 75MHz DC ACCURACY AND PERFORMANCE differential non-linearity integral non-linearity offset error gain error Vref ANALOG INPUTS analog differential input voltage range analog input resistance (single ended) analog input resistance (differential) analog input capacitance (single-ended) ENCODE INPUTS (Universal) VIH VIL differential input swing DIGITAL OUTPUTS output voltage OUTLEV = 1 (open) OUTLEV = 0 (GND) POWER REQUIREMENTS +5V supply current Power dissipation VCC power supply rejection ratio logic LOW logic HIGH logic HIGH fin = 5MHz, Ain = -1dBFS fin = 5MHz, Ain = -1dBFS Full Full Full Full Full Full Full Full Full Full +25°C +25°C +25°C +25°C Full Full Full Full +25°C Full Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C Full Full +25°C 57 65 64 63 64 64 74 74 72 69 65 68 58 85 83 ±0.8 ±2.0 0 1.2 2.37 2.048 500 1000 2 5 dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS LSB LSB mV %FS V Vpp Ω Ω pF V V V V V V mA mW dB 1 59 1 -30 2.2 30 2.6 1 1 0.


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