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U2733B-C Dataheets PDF



Part Number U2733B-C
Manufacturers TEMIC Semiconductors
Logo TEMIC Semiconductors
Description Fractional-N Frequency Synthesizer
Datasheet U2733B-C DatasheetU2733B-C Datasheet (PDF)

www.DataSheet4U.com U2733B-C Fractional-N Frequency Synthesizer for DAB Tuner Description The U2733B-C is a monolithically integrated fractional-N frequency synthesizer circuit fabricated in TEMIC’s advanced UHF5S technology. Designed for applications in DAB receivers, it controls a VCO to synthesize frequencies in the range of 70 to 500 MHz in a 16 kHz raster; four different reference divide factors can be selected. The lock status of the phase detector is indicated at a special output pin, si.

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www.DataSheet4U.com U2733B-C Fractional-N Frequency Synthesizer for DAB Tuner Description The U2733B-C is a monolithically integrated fractional-N frequency synthesizer circuit fabricated in TEMIC’s advanced UHF5S technology. Designed for applications in DAB receivers, it controls a VCO to synthesize frequencies in the range of 70 to 500 MHz in a 16 kHz raster; four different reference divide factors can be selected. The lock status of the phase detector is indicated at a special output pin, six switching outputs can be addressed. An internal frequency doubler provides an output signal having twice the frequency of the reference oscillator. All functions of this IC are controlled by I2C bus. Features D Microprocessor controlled via I2C bus D 4 addresses selectable D Four reference divide factors selectable: 1024, 1120, 1152, 1536 D Effectively D Programmable 15-bit counter 1:2048 to 1:32767 effectively D Three state phase detector with programmable charge pump D Superior phase noise performance D Deactivation of tuning output programmable D 6 switching outputs (open collector) D Reference frequency doubler (open collector output) D Lock status indication (open collector) D Fully compatible to U2753B-C D SSO20 package Block Diagram FDO 10 Frequency doubler x2 Lock detector REF NREF 4 5 Reference counter Three State Phase Detector Fractional N control 2 Prog. charge pump VD 1 PD NFDO 9 3 PLCK 18 RF NRF 17 Prog. 13 Bit counter N/N=1 4 Bit latch 7 Bit latch 2 Bit latch 5 Bit latch MUX MUX I2C Bus – Interface / Control Switches 19 20 6 ADR 7 8 11 12 13 14 15 16 GND VS SCL SDA SWC SWD SWE SWF SWG SWH 12476 Figure 1. Block diagram TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 1 (14) Preliminary Information U2733B-C Pin Description PD VD PLCK REF NREF ADR SCL SDA NFDO FDO 1 2 3 4 5 6 7 8 9 10 12484 20 VS 19 GND 18 RF 17 NRF 16 SWH 15 SWG 14 SWF 13 SWE 12 SWD 11 SWC Figure 2. Pinning Functional Description The U2733B-C is a low power fractional-N frequency synthesizer designed for applications in DAB receivers. Its RF operation range reaches from 70 MHz up to 500 MHz. The device includes input buffers for reference and RF dividers, a reference divider, a programmable RF divider using fractional-N technique, a tri-state phase detector, a programmable charge pump, six switching outputs, a frequency doubler for the reference input signal and a control unit. The control unit has to be accessed by a micro controller via I2C bus. The programming information is stored in a set of internal registers. The basic difference of this circuit from the U2753B-C is the use of a special phase noise shaping technique based on the fractional-N principle which concentrates the ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Pin 1 2 3 4 5 6 7 8 9 Symbol PD VD PLCK REF NREF ADR SCL SDA NFDO FDO 10 11 SWC 12 13 14 15 16 17 18 19 20 SWD SWE SWF SWG SWH NRF RF GND VS Function Three-state charge pump output Active filter output Lock indicating output (open collector) Reference input Reference input (inverted) Address selection Clock (I2C) Data (I2C) Frequency doubler output (inverted, open collector) Frequency doubler output (open collector) Switching output (opencollector) Switching output (open collector) Switching output (open collector) Switching output (open collector) Switching output (open collector) Switching output (open collector) RF input (inverted) RF input Ground Supply voltage phase detector’s phase noise contribution to the spectrum of the controlled VCO at frequency positions where it doesn’t damage the quality of the received DAB signal. In critical locations of the VCO’s frequency spectrum the phase detectors phase noise contribution is reduced by roughly 12 dB. A special property of the transmission technique which is used in DAB is that the phase noise weighting function which measures the influence of the LO’s phase noise to the phase information of the coded signal in a DAB receiver has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines the DAB signal is not disturbed as long as these lines don’t exceed a certain limit. 2 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 U2733B-C For DAB mode I this phase noise weighting function is shown in the following figure: 1,80 1,60 1,40 1,20 PNWF 1,00 0,80 0,60 0,40 0,20 0,00 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 df / Hz 12477 division ratio is either N or N+1 according to the control of a sp.


TLGD175 U2733B-C FHP3194


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