HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM
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HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM
Features
x x
IDT7035S/L
x
x
x
True Dual-Ported memory ...
Description
www.DataSheet4U.com
HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM
Features
x x
IDT7035S/L
x
x
x
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20ns (max.) Low-power operation IDT7035S Active: 800mW (typ.) Standby: 5mW (typ.) IDT7035L Active: 800mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT7035 easily expands data bus width to 36 bits or more
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x x x
x x x x
using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL CEL OEL
LBR CER OER
I/O9L-I/O17L I/O0L-I/O8L
BUSYL
(1,2)
I/O9R-I/O17R I/O Control I/O Control I/O0R-I/O8R
BUSYR
(1,2)
A12L A0L
Address Decoder
13
MEMORY ARRAY
13
Address Decoder
A12R A0R
CEL OEL R/WL SEML (2) INTL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CER OER R/WR SEMR INTR (2)
4088 drw 01
M/S
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.
SEPTE...
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