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AT24C512B Dataheets PDF



Part Number AT24C512B
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description Two-wire Serial EEPROM 512K
Datasheet AT24C512B DatasheetAT24C512B Datasheet (PDF)

www.DataSheet4U.com Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 3.6V) Internally Organized 65,536 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (3.6V), 400 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 128-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: 1,000,000 Write Cycles – .

  AT24C512B   AT24C512B



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www.DataSheet4U.com Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 3.6V) Internally Organized 65,536 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (3.6V), 400 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 128-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: 1,000,000 Write Cycles – Data Retention: 40 Years • Lead-free/Halogen-free Devices Available • 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead LAP and 8-lead SAP Packages • Die Sales: Wafer Form, Waffle Pack and Bumped Die • • • • • • • • • Two-wire Serial EEPROM 512K (65,536 x 8) Description The AT24C512B provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available in a 1.8V (1.8V to 3.6V) version. AT24C512B with Three Device Address Inputs Preliminary Table 1. Pin Configurations Pin Name A0–A2 SDA SCL WP NC Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect A0 A1 A2 GND 8-lead TSSOP 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND 8-lead PDIP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead Leadless Array VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8-lead SAP 8 7 6 5 1 2 3 4 A0 A1 A2 GND Bottom View Bottom View Rev. 5112A–SEEPR–8/05 1 Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage ............................................ 4.3V DC Output Current........................................................ 3.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1. Block Diagram 2 AT24C512B [Preliminary] 5112A–SEEPR–8/05 AT24C512B [Preliminary] Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address. 3 5112A–SEEPR–8/05 Table 2. Pin Capacitance(1) Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V to +3.6V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Table 3. DC Characteristics Applicable over recommen.


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