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WSF128K32-xH2x Dataheets PDF



Part Number WSF128K32-xH2x
Manufacturers White Electronic
Logo White Electronic
Description 128K x 32 SRAM/FLASH MODULE
Datasheet WSF128K32-xH2x DatasheetWSF128K32-xH2x Datasheet (PDF)

www.DataSheet4U.com White Electronic Designs 128KX32 SRAM/FLASH MODULE FEATURES ■ Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH) ■ Packaging: • 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402) ■ 128Kx32 SRAM ■ 128Kx32 5V Flash ■ Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus ■ Low Power CMOS ■ Commercial, Industrial and Military Temperature Ranges ■ TTL Compatible Inputs and Outputs ■ Built-in Decoupling Caps and Multiple Groun.

  WSF128K32-xH2x   WSF128K32-xH2x



Document
www.DataSheet4U.com White Electronic Designs 128KX32 SRAM/FLASH MODULE FEATURES ■ Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH) ■ Packaging: • 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402) ■ 128Kx32 SRAM ■ 128Kx32 5V Flash ■ Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus ■ Low Power CMOS ■ Commercial, Industrial and Military Temperature Ranges ■ TTL Compatible Inputs and Outputs ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Weight - 13 grams typical PRELIMINARY* WSF128K32-XH2X FLASH MEMORY FEATURES ■ 10,000 Erase/Program Cycles ■ Sector Architecture • 8 equal size sectors of 16K bytes each • Any combination of sectors can be concurrently erased. Also supports full chip erase ■ 5 Volt Programming; 5V ± 10% Supply ■ Embedded Erase and Program Algorithms ■ Hardware Write Protection ■ Page Program Operation and Internal Program Control Time. * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. FIG. 1 1 I/O8 I/O9 I/O10 A14 A16 A11 A0 NC I/O0 I/O1 I/O2 11 22 12 PIN CONFIGURATION FOR WSF128K32-XH2X TOP VIEW 23 FWE2 SWE2 GND I/O11 A10 A9 A15 VCC FCS SCS I/O3 33 I/O15 I/O14 I/O13 I/O12 OE NC FWE1 I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 SWE1 A13 A8 I/O16 I/O17 I/O18 44 34 VCC SWE4 FWE4 I/O27 A4 A5 A6 FWE3 SWE3 GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22 I/O21 I/O20 66 OE A0-16 SCS FCS FWE1 SWE1 56 PIN DESCRIPTION D0-31 A0-16 SWE 1-4 SCS OE VCC GND NC FWE1-4 FCS Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select BLOCK DIAGRAM FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 October 2002 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs A BSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Parameter Flash Data Retention Flash Endurance (write/erase cycles) 10 years 10,000 Test OE Capacitance F/S WE 1-4 Capacitance F/S CS Capacitance D0-31 Capacitance Unit V V V A0 - A16 Capacitance Symbol TA T STG VG TJ V CC -0.5 Min -55 -65 -0.5 Max +125 +150 7.0 150 7.0 Unit °C °C V °C V SCS H L L L OE X L H X SWE X H H L WSF128K32-XH2X SRAM TRUTH TABLE Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active NOTE: 1. FCS must remain high when SCS is low. CAPACITANCE (TA = +25°C) Symbol C OE C WE C CS CI /O C AD Condition Max Unit pF pF pF pF pF V IN = 0V, f = 1.0MHz 80 V IN = 0V, f = 1.0MHz 30 V IN = 0V, f = 1.0MHz 50 V IN = 0V, f = 1.0MHz 30 V IN = 0V, f = 1.0MHz 80 NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol V CC V IH V IL Min 4.5 2.2 -0.5 Max 5.5 V CC + 0.3 +0.8 This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash V CC Active Current for Read (1) Flash V CC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low V CC Lock Out Voltage Symbol I LI I LO I CCx32 I SB V OL V OH I CC1 I CC2 V OL V OH1 V OH2 V LKO Conditions V CC = 5.5, V IN = GND to VCC SCS = VIH, OE = VIH, VOUT = GND to VCC SCS = VIL, OE = FCS = VIH, f = 5MHz, V CC = 5.5 FCS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5 I OL = 8mA, V CC = 4.5 I OH = -4.0mA, V CC = 4.5 FCS = VIL, OE = SCS = VIH FCS = VIL, OE = SCS = VIH I OL = 8.0mA, V CC = 4.5 I OH = -2.5 mA, V CC = 4.5 I OH = -100 µA, V CC = 4.5 0.85 x V CC V CC -0.4 3.2 2.4 220 280 0.45 Min Max 10 10 670 80 0.4 Unit µA µA mA mA V V mA mA V V V V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 White Electronic Designs SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output.


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