WSF128K16-xxx

www.DataSheet4U.com WSF128K16-XXX 128Kx16 SRAM/FLASH MODULE, SMD 5962-96900 FEATURES n n n Access Times of 35ns (SRAM) and 70ns (FLASH) n Access Times of 70ns (SRAM) and 120ns (FLASH) n Packaging 66-pin, PGA Type, 1.075 inch square HIP, Hermetic Ceramic HIP (Package 400) 66-pin, PGA Type, 1.185 inch square HIP, Hermetic Ceramic HIP (Package 401) 68 lead, Hermetic CQFP (G1U), 22.4mm (0.880 inch) square (Package 519). Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (Fig. 2) n 128Kx16 SRAM n 128Kx16 5V FLASH n Organized as 128Kx16 of SRAM and 128Kx16 of Flash Memory with separate Data Buses n Both blocks of memory are User Configurable as 256Kx8 n Low Power CMOS n Commercial, Industrial and Military Temperature Ranges n TTL Compatible Inputs and Outputs n n n n Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight WSF128K16-XHX - 13 grams typical WSF128K16-H1X - 13 grams typical WSF128K16-XG1UX - 5 grams typical FLASH MEMORY FEATURES n n 10,000 Erase/Program Cycles Sector Architecture 8 equal size sectors of 16K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase 5 Volt Programming; 5V ± 10% Supply Embedded Erase and Program Algorithms Hardware Write Protection Page Program Operation and Internal Program Control Time. Note: For programming information refer to Flash Programming 1M5 Application Note. FIG.1 PIN CONFIGURATION FOR WSF128K16-XHX A ND WSF128K16-XH1X TOP VIEW FD0-15 SD0-15 A ...