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IDT71P74604 Dataheets PDF



Part Number IDT71P74604
Manufacturers IDT
Logo IDT
Description (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
Datasheet IDT71P74604 DatasheetIDT71P74604 Datasheet (PDF)

www.DataSheet4U.com 18Mb Pipelined QDR™II SRAM Burst of 4 Features x x x x x x Description Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 x x x x x x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus Four word burst data per two clock cycles.

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www.DataSheet4U.com 18Mb Pipelined QDR™II SRAM Burst of 4 Features x x x x x x Description Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 x x x x x x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus Four word burst data per two clock cycles on each port Four word transfers per clock cycle Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package JTAG Interface The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance. Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single SDR address bus with read addresses and write addresses multiplexed. The read and write addresses interleave with each occurring a maximum of every other cycle. In the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. During write operations, the writing of individual bytes may be blocked through the use of byte or nibble write control signals. The QDRII has echo clocks, which provide the user with a clock Functional Block Diagram D (Note1) DATA REG WRITE DRIVER SENSE AMPS OUTPUT REG SA OUTPUT SELECT OUTPUT SELECT (Note2) ADD REG WRITE/READ DECODE (Note2) R W BWx (Note3) CTRL LOGIC 18M MEMORY ARRAY (Note1) Q K K C C CLK GEN SELECT OUTPUT CONTROL CQ CQ 6111 drw16 Notes 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2 signal lines. MARCH 2004 1 ©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6111/00 IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in two word bursts, with addressing capability to the burst level. edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and fa.


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