EDI8L24129V

www.DataSheet4U.com White Electronic Designs 128Kx24 SRAM 3.3 Volt FEATURES 128Kx24 bit CMOS Static Random Access Memory Array Fast Access Times: 10, 12, and 15ns Master Output Enable and Write Control TTL Compatible Inputs and Outputs Fully Static, No Clocks Surface Mount Package 119 Lead BGA (JEDEC MO-163), No. 391 Small Footprint, 14mm x 22mm Multiple Ground Pins for Maximum Noise Immunity Single +3.3V (±5%) Supply Operation DSP Memory Solution Motorola DSP5630xTM Analog Devices SHARCTM EDI8L24129V DESCRIPTION The EDI8L24129VxxBC is a 3.3V, three megabit SRAM constructed with three 128Kx8 die mounted on a multilayer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the EDI8L24129V is ideal for creating a single chip memory solution for the Motorola DSP5630x (Figure 3) or a two chip solution for the Analog Devices SHARCTM DSP (Figure 4). The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. For example, the capacitance load on the data lines for the BGA package is 58% less than a monolithic SOJ solution. The JEDEC Standard 119 lead BGA provides a 44% space savings over using 128Kx8, 300mil wide SOJs and the BGA package has a maximum height of 100 mils compared to 148 mils for the SOJ packages. The BGA package also allows the use of the same manufacturing and inspection techniqu...