EDI2DL32256V

www.DataSheet4U.com EDI2DL32256V 256Kx32 Synchronous Pipline Burst SRAM 3.3V FEATURES s tKHQV times of 3.5, 3.8 and 4.0ns s 166, 150 and 133 MHz clock speed s DSP Memory Solution Texas Instruments’ TMS320C6201 Texas Instruments’ TMS320C67x s Package: 119 pin BGA, JEDEC MO-163 s 3.3V Operating Supply Voltage s 3.5ns Output Enable access time s Single Write Control and Output Enable Lines s Single Chip Enable Line s 56% space savings vs. monolithic TQFPs s Multiple VCC and VSS pins s Reduced inductance and capacitance DESCRIPTION The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline Burst SRAM constructed with two 256Kx16 die mounted on a multi-layer laminate substrate. The device is packaged in a 119 lead, 14mm by 22mm, BGA. It is available with clock speeds of166, 150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing the user to develop a fast external memory for Texas Instruments’ “C6x”. In Burst Mode data from the first memory location is available in three clock cycles, while the subsequent data is available in one clock cycle (3/1/1/1). Subsequent burst addresses are generated by the TMS320C6x DSP. Individual address locations can also be read, allowing one memory access in 3 clock cycles. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE\), burst control input (ADSC\), byte write enables (BW0\ to BW3\) and Write En...