ADSP-TS202S

www.DataSheet4U.com Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File Dual Integer ALUs, providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for System Integration 1149.1 IEEE Compliant JTAG Test Access Port for On-Chip Emulation On-Chip Arbitration for Glueless Multiprocessing TigerSHARC® Embedded Processor ADSP-TS202S KEY BENEFITS Provides High-Performance Static Superscalar DSP Operations, Optimized for Large, Demanding Multiprocessor DSP Applications Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1) Supports Low-Overhead DMA Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, and Other (Multiprocessor) DSPs Eases DSP Programming Through Extremely Flexible Instruction Set and High-Level-Language Friendly DSP Architecture Enables Scalable Multiprocessing Systems With Low Communications Overhead DATA ADDRESS GENERATION 12M BITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CACHE) SOC BUS JTAG JTAG PORT 6 INTEGER J ALU 32 32 INTEGER K ALU 32X32 32 128 32 PROGRAM SEQUENCER ADDR FETCH J-BUS ADDR J-BUS DA...