CY7C1416AV18

www.DataSheet4U.com PRELIMINARY CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 250-MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only Two output clocks (C and C) account for clock skew and flight time mismatching Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–VDD) 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is ass...