56F8023

56F8033/56F8023 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8023 Rev. 6 02/2010 freescale.com Version History Rev. 0 Rev. 1 Rev. 2 Rev. 3 Rev. 4 Rev. 5 Document Revision History Description of Change Initial public release. In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. Changed input propagation delay values in Table 10-20 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum In Table 10-19, changed the maximum ADC internal clock frequency from 8 MHz to 5.33 MHz. Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Corrected pin number labels in Figure 11...