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PI6C105 Dataheets PDF



Part Number PI6C105
Manufacturers Pericom Semiconductor
Logo Pericom Semiconductor
Description Precision Clock Synthesizer
Datasheet PI6C105 DatasheetPI6C105 Datasheet (PDF)

www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C105 Precision Clock Synthesizer for Mobile PCs Fe.

  PI6C105   PI6C105


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www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C105 Precision Clock Synthesizer for Mobile PCs Features • Two copies of CPU clock with VDD of 2.5V ±5% • • • • • • • • • • 100 MHz or 66 MHz operation Six copies PCI clock (synchronous with CPU clock) 3.3V One copy of Ref. clock @ 14.31818 MHz (3.3VTTL) 48 MHz USB Clock, 24 MHz Super I/O clock I2C Serial Configuration Interface Spread Spectrum Modulation for CPUCLK, and PCICLK Low-cost 14.31818 MHz crystal oscillator input Power management control Isolated core VDD, VSS pins for noise reduction 28-pin SSOP and SOIC package (H) Description The PI6C105 is a high-speed, low-noise clock generator designed to work with the PI6C18x family of clock buffers to meet all clock needs for Mobile Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWR_DWN# signal may be used to power down (or up) the system in an orderly manner. Block Diagram Pin Configuration XTAL_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 V SSREF V DDREF REF V DDCPU CPUCLK0 CPUCLK1 V SSCPU V DDCORE V SSCORE PCI_STOP# CPU_STOP# PWR_DWN# S DATA SCLK XTAL_IN XTAL_OUT REF OSC 2 PLL1 DIV 5 CPU_STOP# XTAL_OUT REF V SSPCI PCICLK_F PCICLK1 PCICLK2 Spread# SEL100/66# CPUCLK [0:1] S DATA SCLK PCICLK [1:5] PCICLK3 PCICLK4 28-Pin H 23 22 21 20 19 18 17 16 15 I2 C PCI_STOP# PCICLK_F V DDPCI PCICLK5 V DDP 2 PLL2 48 MHz ÷2 24 MHz 48M/SPREAD# V SSP 2 24M/SEL100/66# 248 PS8316 03/15/99 DataSheet 4 U .com www.DataSheet4U.com Precision Clock Synthesizer for Mobile PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin 1 2 3 4 5,6,7,8,10 9 11 Signal Name XTAL_IN XTAL_O UT VSSPCI PCICLK _F PCICLK [1:5] VDDPCI VDDP2 48 MHz/SPREAD# 12 48 MHz SPREAD# 13 VSSP2 24 MHz/SEL100/66# 14 24 MHz SEL100/66# 15 16 17 18 19 20 21 22 23,24 25 26 27 28 SCLK SDATA PWR_DWN# CPU_STO P# PCI_STO P# VSSCORE VDDCORE VSSCPU CPUCLK [0:1] VDDCPU REF VDDREF VSSREF 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 Qty. 1 1 1 1 5 1 1 14.318 MHz crystal input 14.318 MHz crystal input Ground for PCI clock outputs Free running PCI clock output PCI clock outputs, TTL compatible 3.3V Power for all PCI clock outputs (4,5,6,7,8,10) Power Supply for 24 MHz and 48 MHz outputs 48 MHz output or SPREAD# input. Internal pull up 48 MHz output for USB clock Active lowEnable Spread Spectrum mode, default disable. This is an input sampled during power up. Becomes 48 MHz output after power up Ground for 24 MHz and 48 MHz 24 MHz output or SEL100/66# input, internal pull up 24 MHz output for Super I/O Clock During power up this pin is SEL100/66# input, 24MHz output otherwise. Low = 66MHz, High = 100MHz Serial Clock for I2C interface. Internal Pull Up Serial Data for I2C interface. Internal Pull Up Active Lower Power Down, When active PLLs, crystal, and oscillator is off. CPUCLK s and PCICLK clocks are held low. Internal Pull Up Active Low. Stops all CPU clocks to low state. Internal Pull Up Active Low. Stops all PCICLK clocks to low state, except for PCICLK _F. Internal Pull Up Ground for chip core Power supply for chip core Ground for CPU clock outputs CPU and Host clock outputs 2.5V Power supply for CPU clock outputs 2.5V Buffered crystal output Power Supply for REF outputs Ground for REF outputs D e s cription PI6C105 249 PS8316 03/15/99 DataSheet 4 U .com www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C105 Precision Clock Synthesizer for Mobile PCs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Select Functions SEL100/66# 0 1 Function 66 MHz active 100 MHz active Clock Enable Configuration CPU_S.


ND3139 PI6C105 PRS07


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