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FUJITSU SEMICONDUCTOR
FR50 32-BIT MICROCONTROLLER MB91F367GA/F368GA Datasheet
Release 1.0 10-Apr-2001
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Revision History
Revision 1.0
Date 10-Apr-2001
Item First revision of preliminary datasheet for MB91F367GA and MB91F368GA
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Table of Contents
1 MB91F367GA/F368GA Overview . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MB91F367GA Block Structure . . . . . . . . . . . . . . . . . . . . . . 6 1.2 MB91F368GA Block Structure . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 Pin Assignment MB91F367GA . . . . . . . . . . . . . . . . . . . . . 14 1.6 Pin Assignment MB91F368GA . . . . . . . . . . . . . . . . . . . . . 15 1.7 I/O Pins and Their Functions . . . . . . . . . . . . . . . . . . . . . . . 16 1.8 Flash Memory Mode of MB91F367GA/F368GA . . . . . . . 20 2 Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.1 Flash Control Status Register (FMCS) . . . . . . . . . . . . . . . 22 2.1.2 Flash Wait Control Register (FMWT) . . . . . . . . . . . . . . . 23 2.2 F362 Mode Register (F362MD) . . . . . . . . . . . . . . . . . . . . . 27 2.3 Oscillation stabilization time . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 Subclock RTC32 (CLKR2) . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 IO-Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Power-on-sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Handling of Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 Run Mode Current/Power consumption . . . . . . . . . . . . . . . 36 9.3.1 Logic Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.2 Analog Power Consumption . . . . . . . . . . . . . . . . . . . . . . 37 9.3.3 I/O and SMC Power Consumption . . . . . . . . . . . . . . . . . . 37 9.4 Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5 Clock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 Clock modulator settings . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix A I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Appendix B Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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CHAPTER 1
MB91F367GA/F368GA Overview
This device is available in two options. The difference between these options is as follows:
Feature
MB91F367GA
MB91F368GA
RTC module
connected to 4 MHz oscillator
connected to 32kHz oscillator at pins 27, 28 calibration unit available
See the following chapters for more details:
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1.1
MB91F367GA Block Structure
4 MHz Oscillator Clock Modulator User RAM 16 KB Bit Search Module Boot ROM 2KB F-bus RAM 16 KB Flash Memory 512 KB R-Bus Adapter
SIO Prescaler/ SIO (2ch)
16 32
FR50 Core
Watchdog Timer
32
Instruction RAM 4KB
32
Bus Converter
DMA Controller
32
User Logic Bus Interface
External Interrupt (8 ch)
CAN (2ch)
ADC (8 ch)
U-Timer/ UART (1ch)
I2C
Reload Timer (3ch)
Alarm Comparator
RTC
Power down Reset
ICU (4 ch)
Free Running Counter (2 ch)
OCU (2 ch)
Voltage regulator
Prog. Pulse Generator (4ch)
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1.2
MB91F368GA Block Structure
4 MHz Oscillator Clock Modulator User RAM 16 KB Bit Search Module Boot ROM 2KB F-bus RAM 16 KB Flash Memory 512 KB R-Bus Adapter
SIO Prescaler/ SIO (2ch)
16 32
FR50 Core
Watchdog Timer
32
Instruction RAM 4KB
32
Bus Converter
DMA Controller
32
User Logic Bus Interface
External Interrupt (8 ch)
CAN (2ch)
ADC (8 ch)
32kHz Subclock Calibration unit
U-Timer/ UA.