CY7C1355A

www.DataSheet4U.com CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture Features Zero Bus Latency, no dead cycles between write and read cycles Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 133, 117, and 100 MHz Fast OE access time: 6.5, 7.0, and 7.5ns Internally synchronized registered outputs eliminate the need to control OE 3.3V –5% and +5% power supply 3.3V or 2.5V I/O supply Single WEN (READ/WRITE) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear four-word burst capability Individual byte write (BWa–BWd) control (may be tied LOW) CEN pin to enable clock and suspend operations Three chip enables for simple depth expansion Automatic Power-down feature available using ZZ mode or CE deselect. JTAG boundary scan (except CY7C1357A) Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array) for CY7C1355A, and 100-pin TQFP packages for both devices All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and read-write control (WEN). BWc and BWd apply to CY7C1355A only. Address and control signals are applied to the SRAM during one clock cycle, and on...