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CY7C1386C CY7C1387C
18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Features
• Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) • Depth expansion without wait state • 3.3V –5% and +10% core power supply (VDD) • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • • • • • Intel
Functional Description[1]
The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).
• IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option
The CY7C1386C/CY7C1387C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 225 MHz 2.8 325 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 and CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.
Cypress Semiconductor Corporation Document #: 38-05239 Rev. *B
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3901 North First Street
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San Jose, CA 95134 • 408-943-2600 Revised February 26, 2004
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Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write User-selectable burst counter supporting operations (see Pin Descriptions and Truth Table for further Pentium interleaved or linear burst sequences details). Write cycles can be one to four bytes wide as Separate processor and controller address strobes controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an Synchronous self-timed writes additional pipelined enable register which delays turning off www.DataSheet4U.com Asynchronous output enable the output buffers an additional cycle when a deselect is Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA executed.This feature allows depth expansion without penaland 165-Ball fBGA packages izing system performance.
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CY7C1386C CY7C1387C
1
Logic Block Diagram – CY7C1386C (512K x 36)
A0,A1,A
ADDRESS REGISTER
2 A[1:0]
MODE ADV CLK
BURST LOGIC
Q1
COUNTER AND
CLR ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQc,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA,DQPA BYTE WRITE REGISTER ENABLE REGISTER
Q0
DQD,DQPD BYTE WRITE DRIVER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER DQA,DQPA BYTE WRITE DRIVER
MEMORY ARRAY SENSE AMPS
BWC
OUTPUT REGISTERS
OUTPUT BUFFERS
E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE GW CE1 CE2 CE3 OE
ZZ
2
SLEEP CONTROL
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Logic Block Diagram – CY7C1387C (1M x 18)
A0, A1, A
ADDRESS REGISTER
2 A[1:0]
MODE
ADV CLK
Q1 BURST COUNTER AND LOGIC CLR Q0
ADSC ADSP DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS
BWB
OUTPUT REGISTERS
OUTPUT BUFFERS E
DQs, DQPA DQPB
BWA BWE GW CE1 CE2 CE3 OE
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document #: 38-05239 Rev. *B
Page 2 of 34
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PIPELINED ENABLE
INPUT REGISTERS
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CY7C1386C CY7C1387C
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables)
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ.