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AS4LC1M16S0
(AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
Description
www.DataSheet4U.com May 2001 Preliminary ® 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM Features Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 All signals referenced to positive edge of clock, fully s...
Alliance Semiconductor
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