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SH67P33
OTP 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller ROM: 1K X 16 bits OTP ROM RAM: 48 X 4 bits RAM (Data Memory) Operation voltage: 1.8V - 3.6V (Typical: 3.0V) 16 CMOS bi-directional I/O pins and 1 COMS input pin 4-level subroutine nesting (including interrupts) One 8-bit auto re-loadable timer/counter Warm-up timer for power-on reset Powerful interrupt sources: - Internal interrupt (Timer0). - External interrupts: (rising edge). PORTB & PORTC or PORTB, PORTC & PORTD (Code Option) Remote control programmable carrier synthesizer Oscillator :(Code Option) - External Ceramic Resonator/Crystal Oscillator: 400kHz - 4MHz - Built-in RC Oscillator: 4MHz typical Instruction cycle time: - 4/455kHz (≈ 8.79µs) for 455kHz OSC clock - 4/4MHz (= 1µs) for 4MHz OSC clock Two low power operation modes: HALT and STOP Built-in watchdog timer OTP type/Code protection 20-pin DIP/TSSOP/SOP package
General Description
SH67P33 is dedicated to infrared remote control transmitter applications. This chip integrates the SH6610C 4-bit CPU core with DataSheet4U.com RAM, program ROM, one 8-bit timer, and programmable input/output pins and carrier synthesizer. When in standby function, system will stop oscillator and remain low power dissipation.
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Pin Configuration
GND PORTD.0 PORTD.1 PORTE.0/OSCI PORTE.1/OSCO PORTD.2 PORTC.0 PORTC.1 PORTC.2 PORTC.3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD
REM PORTA.3 PORTA.2 PORTA.1 PORTA.0 PORTB.3 PORTB.2 PORTB.1 PORTB.0
SH67P33
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SH67P33
Block Diagram
OSCI
OSCO
LOW VOLTAGE RESET
OSC
CPU
WATCHDOG
PRESCALER
PORTA (4 BITS) PORTA [0:3] PORTB (4 BITS) PORTB [0:3] PORTC (4 BITS) PORTC [0:3] PORTD (3 BITS)
8-BIT TIMER (UP COUNTER)
CTL REG. PORTE (2 BITS)
PORTD [0:2]
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TIMER INTERRUPT
ROM 1K X 16BIT
PORTE [0:1] REMOTE CONTROL SYNTHESIZER REM
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48 X 4 BIT
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SH67P33
Pin Descriptions
Pin No. 7 - 10 2 3, 6 19 20 4 5 1 15 - 18 11 - 14 Designation PORTC [0:3] PORTD.0 PORTD [1:2] REM VDD PORTE.0/OSCI PORTE.1/OSCO GND PORTA [0:3] PORTB [0:3] I/O I/O I I/O O P I/O I/O P I/O I/O Description Bit programmable I/O pins, Vector Interrupt (Active rising edge) Input pin Bit programmable I/O pins Carrier synthesizer for infrared or RF output pin Power supply Bit programmable I/O pin, shared with oscillator input pin connected to ceramic resonator or crystal oscillator Bit programmable I/O pin, shared with oscillator output pin connected to ceramic resonator or crystal oscillator Ground pin Bit programmable I/O pins Bit programmable I/O pins, Vector Interrupt (Active rising edge)
OTP Programming Pin Description (OTP Program Mode) Pin No. 20 2 1 4 15 Designation VDD VPP GND SCK SDA I/O P P P I I/O Shared by VDD PORTD.0 GND PORTE.0/OSCI PORTA.0 Description Programming Power supply (+5.5V) Programming high voltage Power supply (+11.0V) Ground Programming Clock input pin Programming Data pin
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SH67P33
Functional Description
1. CPU 1.4. Table Branch Register (TBR) The CPU contains the following functional blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Table Data can be stored in program memory and can be Accumulator, Table Branch Register, Data Pointer (INX, referenced by using Table Branch (TJMP) and Return DPH, DPM, and DPL) and Stacks. Constant (RTNW) instructions. The TBR and AC are placed 1.1. PC by an offset address in program ROM. TJMP instruction branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The The PC is used for ROM addressing consisting of 12-bits: address is determined by RTNW to return look-up value into Page Register (PC11), and Ripple Carry Counter (PC10, (TBR, AC). ROM code bit7-bit4 is placed into TBR and PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). bit3-bit0 into AC. The program counter is loaded with data corresponding to 1.5. Data Pointer each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K. The Data Pointer can indirectly address data memory. Pointer address is located in register DPH (3-bits), DPM The program counter cans only 4K program ROM address. (3-bits) and DPL (4-bits). The addressing range can have (Refer to the ROM description). 3FFH locations. Pseudo index address (INX) is used to read 1.2. ALU and CY or write Data memory, then RAM address bit9 - bit0 comes The ALU performs arithmetic and logic operations. The ALU from DPH, DPM and DPL. provides the following functions: 1.6. Stack Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) The stack is a group of registers used to save the contents of Decimal adjustments for addition/subtraction (DAA, DAS) CY & PC (11-0) sequentially with each subroutine call or Logic operations (AND, EOR, .