Document
www.DataSheet4U.com
VIS
Description
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Selfrefresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII.
Features
• Single 5V or 3.3V only power supply • High speed tRAC access time: 50/60ns • Extended-data-out (EDO) page mode access • I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) • 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh • Refresh interval: - RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms - Self-refresh: 1024 cycles • JEDEC standard pinout: 44-pin 400mil SOJ and 50(44)-pin 400mil TSOPII
DataSheet4U.com
DataShee
DataSheet4U.com
Document:1G5-0179 Rev.2 Page 1
DataSheet 4 U .com
www.DataSheet4U.com
VIS
Pin Configuration 42-Pin 400mil SOJ VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
50(44)-Pin 400mil TSOPII
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS
1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26
GND DQ15 DQ14 DQ13 DQ12 GND DQ11 DQ10 DQ9 DQ8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
et4U.com
NC NC WE OE RAS A9 NC A8 NC A7 A0 A1 A6 DataSheet4U.com A2 A5 A3 A4 VCC VSS
DataShee
Pin Description Pin Name A0-A9 Function Address inputs - Row address: A0-A9 - Column address: A0-A9 - Refresh address: A0-A9 Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+5 V or + 3.3V) Ground No connection
DQ0~DQ15 RAS UCAS, LCAS WE OE Vcc Vss NC
DataSheet4U.com
Document:1G5-0179 Rev.2 Page 2
DataSheet 4 U .com
www.DataSheet4U.com
VIS
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
Block Diagram
WE LCAS UCAS CAS
CONTROL LOGIC
DATA - IN BUFFER DQ1 . . DQ16
NO.2 CLOCK GENERATOR
DATA - OUT BUFFER OE
COLUMNADDRESS BUFFERS (10) A0 A2 A3 A4 A5 A6 A7
ROW DECODER
COLUMN DECODER
A1 m et4U.co
REFRESH CONTROLLER
DataSheet4U.com
1024
DataShee
SENSE AMPLIFIERS I/0 GATING REFRESH COUNTER
1024x16
A8 A9 ROW ADDRESS BUFFERS (10)
1024 x 1024 x 16 MEMORY ARRAY
1024
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
DataSheet4U.com
Document:1G5-0179 Rev.2 Page 3
DataSheet 4 U .com
www.DataSheet4U.com
VIS
TRUTH TABLE
FUNCTION RAS STANDBY READ : WORD READ : LOWER BYTE H L L LCAS H→X L L UCAS H→X L H WE X H H OE X L L
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
ADDRESSES ROW X ROW ROW COL X COL COL High-Z Data-Out Lower Byte: Data-Out Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-Out Data-In DQS Notes
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE : UPPER BYTE (EARLY) READ WRITE PAGE-MODE READ 1st Cycle 2nd Cycle PAGE-MODE WRITE 1st Cycle 2nd Cycle PAGE-MODE READWRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE RAS-ONLY REFRESH CBR REFRESH
L
L
L
L
X
ROW
COL
L
L
H
L
X
ROW
COL
Lower Byte: Data-In Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z 4 1,2 2 2 1 1 1,2 1,2 2 1,3
L
H
L
L
X
ROW
COL
L L L L L L L L→H→L L→H→L L H→L
L H→L H→L H→L H→L H→L H→L L L H L
L H→L H→L H→L H→L H→L H→L L L H L
H→L H H L L H→L H→L H L X H
L→H L L X X L→H L→H L X X X
ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X
COL COL COL COL COL COL COL COL COL n/a X
et4U.com
DataSheet4U.com
DataShee
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS).
DataSheet4U.com
Document:1G5-0179 Rev.2 Page 4
DataSheet 4 U .com
www.DataSheet4U.com
VIS
Absolute Maximum Ratings
VG26(V)(S)18165C/VG26(V)(S)18165D 1,048,576 x 16 - Bit CMOS Dynamic RAM
Parameter Symbol 5V 3.3V VT VCC IOUT PD TOPT TSTG Value -1.0 to + 7.0 -0.5 to + 4.6 -1.0 to + 7.0 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125 Unit V
Voltage on an any pin relative to Vss
Supply voltage relative to Vss
5V 3.3V
V mA W
°C °C
Short circuit output current Power dissipation Operating temperature Storage temperature
Recommended DC Operating Conditions
Parame.