CMOS DRAM
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Description The device is CMOS Dynamic RAM organized as 1,048,576 words x 16 bits. It is fabrio...
Description
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VIS
Description The device is CMOS Dynamic RAM organized as 1,048,576 words x 16 bits. It is fabrionly or 3.3V only power supply. Low voltage operation is more suitable to be used on battery
VG26(V)(S)18160CJ 1,048,576 x 16 - Bit CMOS Dynamic RAM
cated with an advanced submicron CMOS technology and designed to operate from a single 5V
backup, portable electronic application. A new refresh feature called “ self-refresh “ is supported and very slow CBR cycles are being performed. It is packaged in JEDEC standard 42 - pin plastic SOJ.
Features Single 5V ( ± 10 %) or 3.3V (+10%,-5%) only power supply High speed tRAC access time : 50/60 ns Low power dissipation - Active mode : 5V version 605/550 mW (Max.) 3.3V version 396/360 mW (Max.) - Standby mode : 5V version 1.375 mW (Max.) 3.3V version 0.54 mW (Max.) Fast Page Mode access I/O level : TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) 1024 refresh cycles in 16 ms (Std) or 128ms (S - version) 4 refresh mode : - RAS only refresh - CAS-before-RAS refresh - Hidden refresh - Self - refresh (S - version)
DataShee
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Document : 1G5-0163 4 U .com DataSheet
Rev.1
Page 1
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Pin Configuration 42-Pin 400mil Plastic SOJ
VG26(V)(S)18160CJ 1,048,576 x 16 - Bit CMOS Dynamic RAM
VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS DQ1...
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