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EP314 Dataheets PDF



Part Number EP314
Manufacturers Altera
Logo Altera
Description (EP312 / EP314) Classic FPLDs
Datasheet EP314 DatasheetEP314 Datasheet (PDF)

www.DataSheet4U.com ® EP312 & EP324 Classic EPLDs Data Sheet April 1995, ver. 1 Features s s s s s s s s s s s s s s High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324) – Combinatorial speeds as fast as 25 ns – Counter frequencies of up to 33.3 MHz – Pipelined data rates of up to 66 MHz Multiple 20-pin PAL and GAL replacement and integration Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements Programmable registers providing D, .

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www.DataSheet4U.com ® EP312 & EP324 Classic EPLDs Data Sheet April 1995, ver. 1 Features s s s s s s s s s s s s s s High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324) – Combinatorial speeds as fast as 25 ns – Counter frequencies of up to 33.3 MHz – Pipelined data rates of up to 66 MHz Multiple 20-pin PAL and GAL replacement and integration Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements Programmable registers providing D, T, JK, and SR flipflops with individual Clear and Clock controls Dual feedback on all macrocells for implementing buried registers with bidirectional I/O Programmable-AND/allocatable-OR structure allowing up to 16 product terms per macrocell DataShee Two product terms on all macrocell control signals Programmable inputs (8 in EP312, 10 in EP324) configurable as DataSheet4U.com latches, registers, or flow-through input Available in windowed ceramic and one-time-programmable (OTP) plastic packages with 24 to 44 pins: – 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) – 28-pin plastic J-lead chip carrier (PLCC) – 40-pin CerDIP and PDIP – 44-pin PLCC One global Clock pin; one global Input Latch Enable/Input Clock/Input (ILE/ICLK/INPUT) pin Programmable “standby” option for low-power operation Programmable Security Bit for total protection of proprietary designs 100% generically testable to provide 100% programming yield Software design support with the Altera PLDshell Plus software and a wide range of third-party tools; programming support through third-party vendors General Description The CMOS EPROM EP312 and EP324 devices have a versatile macrocell structure and I/O architecture, which allow them to implement highperformance logic functions effectively. The EP312 and EP324 input and macrocell features are a superset of features offered by PAL/GAL devices. Therefore, EP312 and EP324 devices can be used as an alternative to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate arrays. 1 DataSheet4U.com Altera Corporation A-DS-312/324.01 DataSheet 4 U .com www.DataSheet4U.com EP312 & EP324 Classic EPLDs EP312 and EP324 devices operate in high-performance systems with low power consumption. The programmable standby function provides “zero” power consumption for applications where performance can be traded for power savings. Functional Description The EP312 and EP324 architecture is based on a sum-of-products programmable-AND/allocatable-OR structure. EP312 and EP324 devices can implement combinatorial and sequential logic functions, as well as combinatorial-register and register-combinatorial-register logic forms, to easily accommodate state machine designs. Figure 1 and Figure 2 show block diagrams of the EP312 and EP324 architectures. The EP312 device contains 12 I/O macrocells and 8 programmable input structures; the EP324 device contains 24 I/O macrocells and 10 programmable input structures. EP312 and EP324 macrocells are divided into 2 rings for product-term allocation. Both devices have 2 additional inputs that can be programmed either as combinatorial inputs or Clock inputs. Each input structure can be individually configured as a latch, register, or flow-through input. Input latches and registers can be clocked synchronously or asynchronously. et4U.com Figure 1. EP312 Block Diagram Clock/Input 1 DataShee DataSheet4U.com Global Clock Input/Register/Latch Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 1 2 3 4 5 6 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Ring 1 Global Bus Global Clock Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 7 8 9 10 11 12 Ring 2 Input Latch Enable/Input Clock/Input 2 DataSheet4U.com 2 Altera Corporation DataSheet 4 U .com www.DataSheet4U.com EP312 & EP324 Classic EPLDs Figure 2. EP324 Block Diagram Input/Register/Latch Clock/Input 1 Global Clock Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Global Bus Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Global Clock Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 17 Macrocell 18 Macrocell 19 Macrocell 20 Macrocell 21 Macrocell 22 Macrocell 23 Macrocell 24 1 2 3 4 5 6 7 8 9 10 11 12 Ring 1 et4U.com DataSheet4U.com 13 14 15 16 17 18 19 20 21 22 23 24 Ring 2 DataShee Input Latch Enable/Input Clock/Input 2 The EP312 and EP324 architectures include the following features: s s s s Macrocells Product-term allocation Programmable inputs Power-on characteristics Macrocells Each EP312 and EP324 macrocell contains 16 product terms (see Figure 3). Half of the product terms are available to support logic functions; half are dedicated to the macrocell control signals. The inputs to the AND array originate from the true and complement signals of the programmable input stru.


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